target/ppc: Add POWER10 exception model
POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], and it removes support for the LPCR[AIL]=0b10 mode. Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20210501072436.145444-3-npiggin@gmail.com> [dwg: Corrected tab indenting] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1396,7 +1396,12 @@ static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu,
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}
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}
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if (mflags == 1) {
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if (mflags == 1) {
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/* AIL=1 is reserved */
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/* AIL=1 is reserved in POWER8/POWER9/POWER10 */
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return H_UNSUPPORTED_FLAG;
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}
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if (mflags == 2 && (pcc->insns_flags2 & PPC2_ISA310)) {
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/* AIL=2 is reserved in POWER10 (ISA v3.1) */
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return H_UNSUPPORTED_FLAG;
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return H_UNSUPPORTED_FLAG;
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}
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}
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@ -116,6 +116,8 @@ enum powerpc_excp_t {
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POWERPC_EXCP_POWER8,
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POWERPC_EXCP_POWER8,
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/* POWER9 exception model */
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/* POWER9 exception model */
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POWERPC_EXCP_POWER9,
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POWERPC_EXCP_POWER9,
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/* POWER10 exception model */
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POWERPC_EXCP_POWER10,
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};
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};
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/*****************************************************************************/
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/*****************************************************************************/
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@ -354,10 +354,11 @@ typedef struct ppc_v3_pate_t {
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#define LPCR_PECE_U_SHIFT (63 - 19)
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#define LPCR_PECE_U_SHIFT (63 - 19)
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#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
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#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
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#define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
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#define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
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#define LPCR_RMLS_SHIFT (63 - 37)
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#define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */
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#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
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#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
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#define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
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#define LPCR_ILE PPC_BIT(38)
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#define LPCR_ILE PPC_BIT(38)
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#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
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#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
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#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
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#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
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#define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
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#define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
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#define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
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#define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
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@ -170,7 +170,27 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
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* +-------------------------------------------------------+
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* +-------------------------------------------------------+
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*
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*
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* The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to
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* The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to
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* the hypervisor in AIL mode if the guest is radix.
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* the hypervisor in AIL mode if the guest is radix. This is good for
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* performance but allows the guest to influence the AIL of hypervisor
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* interrupts using its MSR, and also the hypervisor must disallow guest
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* interrupts (MSR[HV] 0->0) from using AIL if the hypervisor does not want to
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* use AIL for its MSR[HV] 0->1 interrupts.
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*
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* POWER10 addresses those issues with a new LPCR[HAIL] bit that is applied to
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* interrupts that begin execution with MSR[HV]=1 (so both MSR[HV] 0->1 and
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* MSR[HV] 1->1).
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*
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* HAIL=1 is equivalent to AIL=3, for interrupts delivered with MSR[HV]=1.
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*
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* POWER10 behaviour is
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* | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
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* +-----------+------------+-------------+---------+-------------+-----+
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* | a | h | 00/01/10 | 0 | 0 | 0 |
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* | a | h | 11 | 0 | 0 | a |
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* | a | h | x | 0 | 1 | h |
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* | a | h | 00/01/10 | 1 | 1 | 0 |
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* | a | h | 11 | 1 | 1 | h |
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* +--------------------------------------------------------------------+
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*/
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*/
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static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
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static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
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target_ulong msr,
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target_ulong msr,
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@ -213,6 +233,32 @@ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
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/* AIL=1 is reserved, treat it like AIL=0 */
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/* AIL=1 is reserved, treat it like AIL=0 */
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return;
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return;
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}
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}
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} else if (excp_model == POWERPC_EXCP_POWER10) {
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if (!mmu_all_on && !hv_escalation) {
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/*
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* AIL works for HV interrupts even with guest MSR[IR/DR] disabled.
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* Guest->guest and HV->HV interrupts do require MMU on.
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*/
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return;
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}
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if (*new_msr & MSR_HVB) {
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if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) {
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/* HV interrupts depend on LPCR[HAIL] */
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return;
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}
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ail = 3; /* HAIL=1 gives AIL=3 behaviour for HV interrupts */
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} else {
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ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
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}
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if (ail == 0) {
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return;
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}
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if (ail == 1 || ail == 2) {
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/* AIL=1 and AIL=2 are reserved, treat them like AIL=0 */
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return;
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}
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} else {
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} else {
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/* Other processors do not support AIL */
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/* Other processors do not support AIL */
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return;
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return;
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@ -328,7 +374,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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if (excp_model == POWERPC_EXCP_POWER7 ||
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if (excp_model == POWERPC_EXCP_POWER7 ||
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excp_model == POWERPC_EXCP_POWER8 ||
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excp_model == POWERPC_EXCP_POWER8 ||
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excp_model == POWERPC_EXCP_POWER9) {
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excp_model == POWERPC_EXCP_POWER9 ||
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excp_model == POWERPC_EXCP_POWER10) {
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lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
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lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
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} else
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} else
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#endif /* defined(TARGET_PPC64) */
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#endif /* defined(TARGET_PPC64) */
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@ -848,7 +895,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
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} else if (env->spr[SPR_LPCR] & LPCR_ILE) {
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} else if (env->spr[SPR_LPCR] & LPCR_ILE) {
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new_msr |= (target_ulong)1 << MSR_LE;
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new_msr |= (target_ulong)1 << MSR_LE;
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}
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}
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} else if (excp_model == POWERPC_EXCP_POWER9) {
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} else if (excp_model == POWERPC_EXCP_POWER9 ||
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excp_model == POWERPC_EXCP_POWER10) {
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if (new_msr & MSR_HVB) {
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if (new_msr & MSR_HVB) {
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if (env->spr[SPR_HID0] & HID0_POWER9_HILE) {
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if (env->spr[SPR_HID0] & HID0_POWER9_HILE) {
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new_msr |= (target_ulong)1 << MSR_LE;
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new_msr |= (target_ulong)1 << MSR_LE;
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@ -7731,7 +7731,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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if (env->excp_model == POWERPC_EXCP_POWER7 ||
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if (env->excp_model == POWERPC_EXCP_POWER7 ||
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env->excp_model == POWERPC_EXCP_POWER8 ||
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env->excp_model == POWERPC_EXCP_POWER8 ||
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env->excp_model == POWERPC_EXCP_POWER9) {
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env->excp_model == POWERPC_EXCP_POWER9 ||
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env->excp_model == POWERPC_EXCP_POWER10) {
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qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
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qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
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env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
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env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
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}
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}
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@ -9316,7 +9316,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
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pcc->radix_page_info = &POWER10_radix_page_info;
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pcc->radix_page_info = &POWER10_radix_page_info;
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pcc->lrg_decr_bits = 56;
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pcc->lrg_decr_bits = 56;
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#endif
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#endif
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pcc->excp_model = POWERPC_EXCP_POWER9;
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pcc->excp_model = POWERPC_EXCP_POWER10;
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pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
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pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
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pcc->bfd_mach = bfd_mach_ppc64;
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pcc->bfd_mach = bfd_mach_ppc64;
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pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
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pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
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