From f9c481247f6a2c87439e0ebfa42cd56325db2ac0 Mon Sep 17 00:00:00 2001 From: Katsuhiro Ueno Date: Tue, 27 Apr 2021 11:02:46 +0900 Subject: [PATCH 1/3] hw/input/hid: Add support for keys of jp106 keyboard. Add support for the following keys: KATAKANAHIRAGANA, HENKAN, MUHENKAN, RO, and YEN. Before this commit, these keys did not work as expected when a jp106 keyboard was connected to the guest as a usb-kbd device. Signed-off-by: Katsuhiro Ueno Message-Id: Signed-off-by: Gerd Hoffmann --- hw/input/hid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/input/hid.c b/hw/input/hid.c index e1d2e46083..8aab0521f4 100644 --- a/hw/input/hid.c +++ b/hw/input/hid.c @@ -51,8 +51,8 @@ static const uint8_t hid_usage_keys[0x100] = { 0x45, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0xe8, 0xe9, 0x71, 0x72, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0xe3, 0xe7, 0x65, + 0x88, 0x00, 0x00, 0x87, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x8a, 0x00, 0x8b, 0x00, 0x89, 0xe7, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, From 3c6151cd11ae7e4a7dae10f8c17ab1fe2f0a73bf Mon Sep 17 00:00:00 2001 From: Ruimei Yan Date: Fri, 21 May 2021 10:42:23 +0800 Subject: [PATCH 2/3] hw/usb: hcd-xhci-pci: Raise MSI/MSI-X interrupts only when told to MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit At present MSI / MSI-X interrupts are triggered regardless of the irq level. We should have checked the level to determine whether the interrupt needs to be delivered. The level check logic was present in early versions of the xhci model, but got dropped later by a rework of interrupt handling under commit 4c4abe7cc903 ("xhci: rework interrupt handling"). Fixes: 4c4abe7cc903 ("xhci: rework interrupt handling") Signed-off-by: Ruimei Yan Signed-off-by: Bin Meng Message-Id: <20210521024224.2277634-1-bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci-pci.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c index 9421734d0f..b6acd1790c 100644 --- a/hw/usb/hcd-xhci-pci.c +++ b/hw/usb/hcd-xhci-pci.c @@ -67,12 +67,13 @@ static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) msi_enabled(pci_dev))) { pci_set_irq(pci_dev, level); } - if (msix_enabled(pci_dev)) { + + if (msix_enabled(pci_dev) && level) { msix_notify(pci_dev, n); return; } - if (msi_enabled(pci_dev)) { + if (msi_enabled(pci_dev) && level) { msi_notify(pci_dev, n); return; } From fc967aad408eb4777b099d17ada1f39be5f6fd2e Mon Sep 17 00:00:00 2001 From: Ruimei Yan Date: Fri, 21 May 2021 10:42:24 +0800 Subject: [PATCH 3/3] hw/usb: hcd-xhci-pci: Fix spec violation of IP flag for MSI/MSI-X MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Per xHCI spec v1.2 chapter 4.17.5 page 296: If MSI or MSI-X interrupts are enabled, Interrupt Pending (IP) shall be cleared automatically when the PCI dword write generated by the interrupt assertion is complete. Currently QEMU does not clear the IP flag in the MSI / MSI-X mode. This causes subsequent spurious interrupt to be delivered to guests. To solve this, we change the xhci intr_raise() hook routine to have a bool return value that is passed to its caller (the xhci core), with true indicating that IP should be self-cleared. Fixes: 62c6ae04cf43 ("xhci: Initial xHCI implementation") Fixes: 4c47f800631a ("xhci: add msix support") Signed-off-by: Ruimei Yan [bmeng: move IP clear codes from xhci pci to xhci core] Signed-off-by: Bin Meng Message-Id: <20210521024224.2277634-2-bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci-pci.c | 8 +++++--- hw/usb/hcd-xhci-sysbus.c | 4 +++- hw/usb/hcd-xhci.c | 8 ++++++-- hw/usb/hcd-xhci.h | 2 +- 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c index b6acd1790c..e934b1a5b1 100644 --- a/hw/usb/hcd-xhci-pci.c +++ b/hw/usb/hcd-xhci-pci.c @@ -57,7 +57,7 @@ static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable) } } -static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) +static bool xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) { XHCIPciState *s = container_of(xhci, XHCIPciState, xhci); PCIDevice *pci_dev = PCI_DEVICE(s); @@ -70,13 +70,15 @@ static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) if (msix_enabled(pci_dev) && level) { msix_notify(pci_dev, n); - return; + return true; } if (msi_enabled(pci_dev) && level) { msi_notify(pci_dev, n); - return; + return true; } + + return false; } static void xhci_pci_reset(DeviceState *dev) diff --git a/hw/usb/hcd-xhci-sysbus.c b/hw/usb/hcd-xhci-sysbus.c index 42e2574c82..a14e438196 100644 --- a/hw/usb/hcd-xhci-sysbus.c +++ b/hw/usb/hcd-xhci-sysbus.c @@ -16,11 +16,13 @@ #include "hw/acpi/aml-build.h" #include "hw/irq.h" -static void xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level) +static bool xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level) { XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci); qemu_set_irq(s->irq[n], level); + + return false; } void xhci_sysbus_reset(DeviceState *dev) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 46212b1e69..e01700039b 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -551,7 +551,9 @@ static void xhci_intr_update(XHCIState *xhci, int v) level = 1; } if (xhci->intr_raise) { - xhci->intr_raise(xhci, 0, level); + if (xhci->intr_raise(xhci, 0, level)) { + xhci->intr[0].iman &= ~IMAN_IP; + } } } if (xhci->intr_update) { @@ -579,7 +581,9 @@ static void xhci_intr_raise(XHCIState *xhci, int v) return; } if (xhci->intr_raise) { - xhci->intr_raise(xhci, v, true); + if (xhci->intr_raise(xhci, v, true)) { + xhci->intr[v].iman &= ~IMAN_IP; + } } } diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h index 7bba361f3b..98f598382a 100644 --- a/hw/usb/hcd-xhci.h +++ b/hw/usb/hcd-xhci.h @@ -194,7 +194,7 @@ typedef struct XHCIState { uint32_t flags; uint32_t max_pstreams_mask; void (*intr_update)(XHCIState *s, int n, bool enable); - void (*intr_raise)(XHCIState *s, int n, bool level); + bool (*intr_raise)(XHCIState *s, int n, bool level); DeviceState *hostOpaque; /* Operational Registers */