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target/arm: Flush high bits of sve register after AdvSIMD INS 

Writes to AdvSIMD registers flush the bits above 128.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214194643.23317-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-14 11:46:43 -08:00 committed by Peter Maydell
parent 33649de62e
commit 528dc354b6
1 changed files with 6 additions and 0 deletions
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6
target/arm/translate-a64.c
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@ -7412,6 +7412,9 @@ static void handle_simd_inse(DisasContext *s, int rd, int rn,
write_vec_element(s, tmp, rd, dst_index, size);
tcg_temp_free_i64(tmp);
/* INS is considered a 128-bit write for SVE. */
clear_vec_high(s, true, rd);
}
@ -7441,6 +7444,9 @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
idx = extract32(imm5, 1 + size, 4 - size);
write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
/* INS is considered a 128-bit write for SVE. */
clear_vec_high(s, true, rd);
}
/*