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pcie_root_port: Add hotplug disabling option

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Make hot-plug/hot-unplug on PCIe Root Ports optional to allow libvirt
manage it and restrict unplug for the whole machine. This is going to
prevent user-initiated unplug in guests (Windows mostly).
Hotplug is enabled by default.
Usage:
    -device pcie-root-port,hotplug=off,...

If you want to disable hot-unplug on some downstream ports of one
switch, disable hot-unplug on PCIe Root Port connected to the upstream
port as well as on the selected downstream ports.

Discussion related:
    https://lists.gnu.org/archive/html/qemu-devel/2020-02/msg00530.html

Signed-off-by: Julia Suvorova <jusual@redhat.com>
Message-Id: <20200226174607.205941-1-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
This commit is contained in:
Julia Suvorova 2020-02-26 18:46:07 +01:00 committed by Michael S. Tsirkin
parent 67f17e23ba
commit 530a096318
6 changed files with 14 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/pci-bridge/pcie_root_port.c
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@ -94,7 +94,7 @@ static void rp_realize(PCIDevice *d, Error **errp)
pcie_cap_arifwd_init(d); pcie_cap_arifwd_init(d);
pcie_cap_deverr_init(d); pcie_cap_deverr_init(d);
pcie_cap_slot_init(d, s->slot); pcie_cap_slot_init(d, s);
pcie_cap_root_init(d); pcie_cap_root_init(d);
pcie_chassis_create(s->chassis); pcie_chassis_create(s->chassis);

2
hw/pci-bridge/xio3130_downstream.c
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@ -94,7 +94,7 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
} }
pcie_cap_flr_init(d); pcie_cap_flr_init(d);
pcie_cap_deverr_init(d); pcie_cap_deverr_init(d);
pcie_cap_slot_init(d, s->slot); pcie_cap_slot_init(d, s);
pcie_cap_arifwd_init(d); pcie_cap_arifwd_init(d);
pcie_chassis_create(s->chassis); pcie_chassis_create(s->chassis);

11
hw/pci/pcie.c
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@ -495,7 +495,7 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
/* pci express slot for pci express root/downstream port /* pci express slot for pci express root/downstream port
PCI express capability slot registers */ PCI express capability slot registers */
void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s)
{ {
uint32_t pos = dev->exp.exp_cap; uint32_t pos = dev->exp.exp_cap;
@ -505,13 +505,16 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP, pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
~PCI_EXP_SLTCAP_PSN); ~PCI_EXP_SLTCAP_PSN);
pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
(slot << PCI_EXP_SLTCAP_PSN_SHIFT) | (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
PCI_EXP_SLTCAP_EIP | PCI_EXP_SLTCAP_EIP |
PCI_EXP_SLTCAP_HPS |
PCI_EXP_SLTCAP_HPC |
PCI_EXP_SLTCAP_PIP | PCI_EXP_SLTCAP_PIP |
PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_AIP |
PCI_EXP_SLTCAP_ABP); PCI_EXP_SLTCAP_ABP);
if (s->hotplug) {
pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
PCI_EXP_SLTCAP_HPS |
PCI_EXP_SLTCAP_HPC);
}
if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,

1
hw/pci/pcie_port.c
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@ -147,6 +147,7 @@ static const TypeInfo pcie_port_type_info = {
static Property pcie_slot_props[] = { static Property pcie_slot_props[] = {
DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
DEFINE_PROP_BOOL("hotplug", PCIESlot, hotplug, true),
DEFINE_PROP_END_OF_LIST() DEFINE_PROP_END_OF_LIST()
}; };

2
include/hw/pci/pcie.h
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@ -104,7 +104,7 @@ void pcie_cap_deverr_reset(PCIDevice *dev);
void pcie_cap_lnkctl_init(PCIDevice *dev); void pcie_cap_lnkctl_init(PCIDevice *dev);
void pcie_cap_lnkctl_reset(PCIDevice *dev); void pcie_cap_lnkctl_reset(PCIDevice *dev);
void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot); void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s);
void pcie_cap_slot_reset(PCIDevice *dev); void pcie_cap_slot_reset(PCIDevice *dev);
void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta); void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta);
void pcie_cap_slot_write_config(PCIDevice *dev, void pcie_cap_slot_write_config(PCIDevice *dev,

3
include/hw/pci/pcie_port.h
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@ -55,6 +55,9 @@ struct PCIESlot {
/* Disable ACS (really for a pcie_root_port) */ /* Disable ACS (really for a pcie_root_port) */
bool disable_acs; bool disable_acs;
/* Indicates whether hot-plug is enabled on the slot */
bool hotplug;
QLIST_ENTRY(PCIESlot) next; QLIST_ENTRY(PCIESlot) next;
}; };