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More Context/Xcontext fixes. Ifdef some 64bit-only ops, they may 

end up empty for 32bit mips, which dyngen trips over.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2648 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-04-11 02:13:00 +00:00
parent e9df014c0b
commit 534ce69ff0
2 changed files with 10 additions and 10 deletions
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14
target-mips/op.c
View File

@ -1293,7 +1293,7 @@ void op_mtc0_entrylo1 (void)
void op_mtc0_context (void)
{
env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & ~0x007FFFFF);
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
RETURN();
}
@ -1458,12 +1458,6 @@ void op_mtc0_watchhi0 (void)
RETURN();
}
void op_mtc0_xcontext (void)
{
env->CP0_XContext = (int32_t)T0; /* XXX */
RETURN();
}
void op_mtc0_framemask (void)
{
env->CP0_Framemask = T0; /* XXX */
@ -1528,6 +1522,7 @@ void op_mtc0_desave (void)
RETURN();
}
#ifdef TARGET_MIPS64
void op_dmfc0_entrylo0 (void)
{
T0 = env->CP0_EntryLo0;
@ -1612,7 +1607,7 @@ void op_dmtc0_entrylo1 (void)
void op_dmtc0_context (void)
{
env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
RETURN();
}
@ -1632,7 +1627,7 @@ void op_dmtc0_watchlo0 (void)
void op_dmtc0_xcontext (void)
{
env->CP0_XContext = T0; /* XXX */
env->CP0_XContext = (env->CP0_XContext & 0xffffffff) | (T0 & ~0xffffffff);
RETURN();
}
@ -1647,6 +1642,7 @@ void op_dmtc0_errorepc (void)
env->CP0_ErrorEPC = T0;
RETURN();
}
#endif /* TARGET_MIPS64 */
#if 0
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)

6
target-mips/translate.c
View File

@ -2750,7 +2750,7 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel)
switch (sel) {
case 0:
/* 64 bit MMU only */
gen_op_mtc0_xcontext();
/* Nothing writable in lower 32 bits */
rn = "XContext";
break;
default:
@ -2946,6 +2946,7 @@ die:
generate_exception(ctx, EXCP_RI);
}
#ifdef TARGET_MIPS64
static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
{
const char *rn = "invalid";
@ -4120,6 +4121,7 @@ die:
#endif
generate_exception(ctx, EXCP_RI);
}
#endif /* TARGET_MIPS64 */
static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
{
@ -4140,6 +4142,7 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
gen_mtc0(ctx, rd, ctx->opcode & 0x7);
opn = "mtc0";
break;
#ifdef TARGET_MIPS64
case OPC_DMFC0:
if (rt == 0) {
/* Treat as NOP */
@ -4154,6 +4157,7 @@ static void gen_cp0 (DisasContext *ctx, uint32_t opc, int rt, int rd)
gen_dmtc0(ctx, rd, ctx->opcode & 0x7);
opn = "dmtc0";
break;
#endif
#if defined(MIPS_USES_R4K_TLB)
case OPC_TLBWI:
gen_op_tlbwi();