target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_*
Convert away from the old interface with the implicit MemOp argument. Importantly, this removes some incorrect casts generated by idef-parser's gen_load(). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230502135741.1158035-4-richard.henderson@linaro.org>
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@ -320,14 +320,14 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
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static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
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static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
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{
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{
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tcg_gen_qemu_ld32u(dest, vaddr, mem_index);
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tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL);
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tcg_gen_mov_tl(hex_llsc_addr, vaddr);
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tcg_gen_mov_tl(hex_llsc_addr, vaddr);
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tcg_gen_mov_tl(hex_llsc_val, dest);
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tcg_gen_mov_tl(hex_llsc_val, dest);
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}
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}
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static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
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static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
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{
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{
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tcg_gen_qemu_ld64(dest, vaddr, mem_index);
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tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ);
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tcg_gen_mov_tl(hex_llsc_addr, vaddr);
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tcg_gen_mov_tl(hex_llsc_addr, vaddr);
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tcg_gen_mov_i64(hex_llsc_val_i64, dest);
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tcg_gen_mov_i64(hex_llsc_val_i64, dest);
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}
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}
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@ -678,7 +678,7 @@ static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA)
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{
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{
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Insn *insn = ctx->insn; /* Needed for CHECK_NOSHUF */
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Insn *insn = ctx->insn; /* Needed for CHECK_NOSHUF */
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CHECK_NOSHUF(EA, 8);
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CHECK_NOSHUF(EA, 8);
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tcg_gen_qemu_ld64(frame, EA, ctx->mem_idx);
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tcg_gen_qemu_ld_i64(frame, EA, ctx->mem_idx, MO_TEUQ);
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}
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}
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static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src)
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static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src)
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@ -1019,7 +1019,7 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src,
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tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1));
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tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1));
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}
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}
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for (int i = 0; i < sizeof(MMVector) / 8; i++) {
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for (int i = 0; i < sizeof(MMVector) / 8; i++) {
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tcg_gen_qemu_ld64(tmp, src, ctx->mem_idx);
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tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ);
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tcg_gen_addi_tl(src, src, 8);
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tcg_gen_addi_tl(src, src, 8);
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tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8);
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tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8);
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}
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}
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@ -1737,36 +1737,34 @@ void gen_load_cancel(Context *c, YYLTYPE *locp)
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void gen_load(Context *c, YYLTYPE *locp, HexValue *width,
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void gen_load(Context *c, YYLTYPE *locp, HexValue *width,
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HexSignedness signedness, HexValue *ea, HexValue *dst)
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HexSignedness signedness, HexValue *ea, HexValue *dst)
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{
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{
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char size_suffix[4] = {0};
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unsigned dst_bit_width;
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const char *sign_suffix;
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unsigned src_bit_width;
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/* Memop width is specified in the load macro */
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/* Memop width is specified in the load macro */
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assert_signedness(c, locp, signedness);
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assert_signedness(c, locp, signedness);
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sign_suffix = (width->imm.value > 4)
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? ""
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: ((signedness == UNSIGNED) ? "u" : "s");
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/* If dst is a variable, assert that is declared and load the type info */
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/* If dst is a variable, assert that is declared and load the type info */
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if (dst->type == VARID) {
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if (dst->type == VARID) {
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find_variable(c, locp, dst, dst);
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find_variable(c, locp, dst, dst);
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}
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}
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snprintf(size_suffix, 4, "%" PRIu64, width->imm.value * 8);
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src_bit_width = width->imm.value * 8;
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dst_bit_width = MAX(dst->bit_width, 32);
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/* Lookup the effective address EA */
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/* Lookup the effective address EA */
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find_variable(c, locp, ea, ea);
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find_variable(c, locp, ea, ea);
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OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
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OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
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OUT(c, locp, "probe_noshuf_load(", ea, ", ", width, ", ctx->mem_idx);\n");
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OUT(c, locp, "probe_noshuf_load(", ea, ", ", width, ", ctx->mem_idx);\n");
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OUT(c, locp, "process_store(ctx, 1);\n");
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OUT(c, locp, "process_store(ctx, 1);\n");
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OUT(c, locp, "}\n");
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OUT(c, locp, "}\n");
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OUT(c, locp, "tcg_gen_qemu_ld", size_suffix, sign_suffix);
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OUT(c, locp, "tcg_gen_qemu_ld_i", &dst_bit_width);
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OUT(c, locp, "(");
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OUT(c, locp, "(");
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if (dst->bit_width > width->imm.value * 8) {
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OUT(c, locp, dst, ", ", ea, ", ctx->mem_idx, MO_", &src_bit_width);
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/*
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if (signedness == SIGNED) {
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* Cast to the correct TCG type if necessary, to avoid implict cast
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OUT(c, locp, " | MO_SIGN");
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* warnings. This is needed when the width of the destination var is
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* larger than the size of the requested load.
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*/
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OUT(c, locp, "(TCGv) ");
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}
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}
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OUT(c, locp, dst, ", ", ea, ", ctx->mem_idx);\n");
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OUT(c, locp, " | MO_TE);\n");
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}
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}
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void gen_store(Context *c, YYLTYPE *locp, HexValue *width, HexValue *ea,
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void gen_store(Context *c, YYLTYPE *locp, HexValue *width, HexValue *ea,
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@ -99,37 +99,37 @@
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#define MEM_LOAD1s(DST, VA) \
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#define MEM_LOAD1s(DST, VA) \
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do { \
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do { \
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CHECK_NOSHUF(VA, 1); \
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CHECK_NOSHUF(VA, 1); \
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tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \
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tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \
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} while (0)
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} while (0)
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#define MEM_LOAD1u(DST, VA) \
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#define MEM_LOAD1u(DST, VA) \
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do { \
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do { \
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CHECK_NOSHUF(VA, 1); \
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CHECK_NOSHUF(VA, 1); \
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tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \
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tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \
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} while (0)
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} while (0)
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#define MEM_LOAD2s(DST, VA) \
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#define MEM_LOAD2s(DST, VA) \
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do { \
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do { \
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CHECK_NOSHUF(VA, 2); \
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CHECK_NOSHUF(VA, 2); \
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tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \
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tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESW); \
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} while (0)
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} while (0)
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#define MEM_LOAD2u(DST, VA) \
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#define MEM_LOAD2u(DST, VA) \
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do { \
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do { \
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CHECK_NOSHUF(VA, 2); \
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CHECK_NOSHUF(VA, 2); \
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tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \
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tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUW); \
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} while (0)
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} while (0)
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#define MEM_LOAD4s(DST, VA) \
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#define MEM_LOAD4s(DST, VA) \
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do { \
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do { \
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CHECK_NOSHUF(VA, 4); \
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CHECK_NOSHUF(VA, 4); \
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tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
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tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESL); \
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} while (0)
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} while (0)
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#define MEM_LOAD4u(DST, VA) \
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#define MEM_LOAD4u(DST, VA) \
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do { \
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do { \
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CHECK_NOSHUF(VA, 4); \
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CHECK_NOSHUF(VA, 4); \
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tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
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tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUL); \
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} while (0)
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} while (0)
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#define MEM_LOAD8u(DST, VA) \
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#define MEM_LOAD8u(DST, VA) \
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do { \
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do { \
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CHECK_NOSHUF(VA, 8); \
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CHECK_NOSHUF(VA, 8); \
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tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \
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tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TEUQ); \
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} while (0)
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} while (0)
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#define MEM_STORE1_FUNC(X) \
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#define MEM_STORE1_FUNC(X) \
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@ -627,27 +627,27 @@ void process_store(DisasContext *ctx, int slot_num)
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switch (ctx->store_width[slot_num]) {
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switch (ctx->store_width[slot_num]) {
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case 1:
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case 1:
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gen_check_store_width(ctx, slot_num);
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gen_check_store_width(ctx, slot_num);
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tcg_gen_qemu_st8(hex_store_val32[slot_num],
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tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
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hex_store_addr[slot_num],
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hex_store_addr[slot_num],
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ctx->mem_idx);
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ctx->mem_idx, MO_UB);
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break;
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break;
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case 2:
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case 2:
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gen_check_store_width(ctx, slot_num);
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gen_check_store_width(ctx, slot_num);
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tcg_gen_qemu_st16(hex_store_val32[slot_num],
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tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
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hex_store_addr[slot_num],
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hex_store_addr[slot_num],
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ctx->mem_idx);
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ctx->mem_idx, MO_TEUW);
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break;
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break;
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case 4:
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case 4:
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gen_check_store_width(ctx, slot_num);
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gen_check_store_width(ctx, slot_num);
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tcg_gen_qemu_st32(hex_store_val32[slot_num],
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tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
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hex_store_addr[slot_num],
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hex_store_addr[slot_num],
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ctx->mem_idx);
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ctx->mem_idx, MO_TEUL);
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break;
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break;
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case 8:
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case 8:
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gen_check_store_width(ctx, slot_num);
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gen_check_store_width(ctx, slot_num);
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tcg_gen_qemu_st64(hex_store_val64[slot_num],
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tcg_gen_qemu_st_i64(hex_store_val64[slot_num],
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hex_store_addr[slot_num],
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hex_store_addr[slot_num],
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ctx->mem_idx);
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ctx->mem_idx, MO_TEUQ);
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break;
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break;
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default:
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default:
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{
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{
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@ -693,13 +693,13 @@ static void process_dczeroa(DisasContext *ctx)
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TCGv_i64 zero = tcg_constant_i64(0);
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TCGv_i64 zero = tcg_constant_i64(0);
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tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f);
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tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f);
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tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
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tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
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tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
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tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
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tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
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}
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}
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}
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}
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