target/arm: Move get_phys_addr_v6 to ptw.c
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
f2d2f5ceb8
commit
53c038efb7
@ -10631,7 +10631,7 @@ int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap, int domain_prot)
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* @ap: The 2-bit simple AP (AP[2:1])
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* @is_user: TRUE if accessing from PL0
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*/
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static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
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int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
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{
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switch (ap) {
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case 0:
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@ -10647,12 +10647,6 @@ static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
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}
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}
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static inline int
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simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
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{
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return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
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}
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/* Translate S2 section/page access permissions to protection flags
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*
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* @env: CPUARMState
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@ -10939,159 +10933,6 @@ uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
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return 0;
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}
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bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
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target_ulong *page_size, ARMMMUFaultInfo *fi)
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{
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CPUState *cs = env_cpu(env);
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ARMCPU *cpu = env_archcpu(env);
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int level = 1;
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uint32_t table;
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uint32_t desc;
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uint32_t xn;
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uint32_t pxn = 0;
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int type;
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int ap;
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int domain = 0;
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int domain_prot;
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hwaddr phys_addr;
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uint32_t dacr;
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bool ns;
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/* Pagetable walk. */
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/* Lookup l1 descriptor. */
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if (!get_level1_table_address(env, mmu_idx, &table, address)) {
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/* Section translation fault if page walk is disabled by PD0 or PD1 */
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fi->type = ARMFault_Translation;
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goto do_fault;
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}
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desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
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mmu_idx, fi);
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if (fi->type != ARMFault_None) {
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goto do_fault;
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}
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type = (desc & 3);
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if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
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/* Section translation fault, or attempt to use the encoding
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* which is Reserved on implementations without PXN.
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*/
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fi->type = ARMFault_Translation;
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goto do_fault;
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}
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if ((type == 1) || !(desc & (1 << 18))) {
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/* Page or Section. */
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domain = (desc >> 5) & 0x0f;
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}
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if (regime_el(env, mmu_idx) == 1) {
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dacr = env->cp15.dacr_ns;
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} else {
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dacr = env->cp15.dacr_s;
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}
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if (type == 1) {
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level = 2;
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}
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domain_prot = (dacr >> (domain * 2)) & 3;
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if (domain_prot == 0 || domain_prot == 2) {
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/* Section or Page domain fault */
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fi->type = ARMFault_Domain;
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goto do_fault;
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}
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if (type != 1) {
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if (desc & (1 << 18)) {
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/* Supersection. */
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phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
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phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
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phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
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*page_size = 0x1000000;
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} else {
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/* Section. */
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phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
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*page_size = 0x100000;
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}
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ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
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xn = desc & (1 << 4);
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pxn = desc & 1;
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ns = extract32(desc, 19, 1);
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} else {
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if (cpu_isar_feature(aa32_pxn, cpu)) {
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pxn = (desc >> 2) & 1;
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}
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ns = extract32(desc, 3, 1);
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/* Lookup l2 entry. */
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table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
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desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
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mmu_idx, fi);
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if (fi->type != ARMFault_None) {
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goto do_fault;
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}
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ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
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switch (desc & 3) {
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case 0: /* Page translation fault. */
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fi->type = ARMFault_Translation;
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goto do_fault;
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case 1: /* 64k page. */
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phys_addr = (desc & 0xffff0000) | (address & 0xffff);
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xn = desc & (1 << 15);
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*page_size = 0x10000;
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break;
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case 2: case 3: /* 4k page. */
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phys_addr = (desc & 0xfffff000) | (address & 0xfff);
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xn = desc & 1;
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*page_size = 0x1000;
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break;
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default:
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/* Never happens, but compiler isn't smart enough to tell. */
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g_assert_not_reached();
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}
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}
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if (domain_prot == 3) {
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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} else {
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if (pxn && !regime_is_user(env, mmu_idx)) {
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xn = 1;
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}
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if (xn && access_type == MMU_INST_FETCH) {
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fi->type = ARMFault_Permission;
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goto do_fault;
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}
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if (arm_feature(env, ARM_FEATURE_V6K) &&
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(regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
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/* The simplified model uses AP[0] as an access control bit. */
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if ((ap & 1) == 0) {
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/* Access flag fault. */
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fi->type = ARMFault_AccessFlag;
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goto do_fault;
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}
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*prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
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} else {
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*prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
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}
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if (*prot && !xn) {
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*prot |= PAGE_EXEC;
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}
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if (!(*prot & (1 << access_type))) {
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/* Access permission fault. */
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fi->type = ARMFault_Permission;
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goto do_fault;
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}
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}
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if (ns) {
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/* The NS bit will (as required by the architecture) have no effect if
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* the CPU doesn't support TZ or this is a non-secure translation
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* regime, because the attribute will already be non-secure.
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*/
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attrs->secure = false;
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}
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*phys_ptr = phys_addr;
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return false;
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do_fault:
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fi->domain = domain;
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fi->level = level;
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return true;
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}
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/*
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* check_s2_mmu_setup
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* @cpu: ARMCPU
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153
target/arm/ptw.c
153
target/arm/ptw.c
@ -136,6 +136,159 @@ do_fault:
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return true;
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}
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static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
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target_ulong *page_size, ARMMMUFaultInfo *fi)
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{
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CPUState *cs = env_cpu(env);
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ARMCPU *cpu = env_archcpu(env);
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int level = 1;
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uint32_t table;
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uint32_t desc;
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uint32_t xn;
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uint32_t pxn = 0;
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int type;
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int ap;
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int domain = 0;
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int domain_prot;
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hwaddr phys_addr;
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uint32_t dacr;
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bool ns;
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/* Pagetable walk. */
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/* Lookup l1 descriptor. */
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if (!get_level1_table_address(env, mmu_idx, &table, address)) {
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/* Section translation fault if page walk is disabled by PD0 or PD1 */
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fi->type = ARMFault_Translation;
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goto do_fault;
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}
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desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
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mmu_idx, fi);
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if (fi->type != ARMFault_None) {
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goto do_fault;
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}
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type = (desc & 3);
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if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
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/* Section translation fault, or attempt to use the encoding
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* which is Reserved on implementations without PXN.
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*/
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fi->type = ARMFault_Translation;
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goto do_fault;
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}
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if ((type == 1) || !(desc & (1 << 18))) {
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/* Page or Section. */
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domain = (desc >> 5) & 0x0f;
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}
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if (regime_el(env, mmu_idx) == 1) {
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dacr = env->cp15.dacr_ns;
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} else {
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dacr = env->cp15.dacr_s;
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}
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if (type == 1) {
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level = 2;
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}
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domain_prot = (dacr >> (domain * 2)) & 3;
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if (domain_prot == 0 || domain_prot == 2) {
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/* Section or Page domain fault */
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fi->type = ARMFault_Domain;
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goto do_fault;
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}
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if (type != 1) {
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if (desc & (1 << 18)) {
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/* Supersection. */
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phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
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phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
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phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
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*page_size = 0x1000000;
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} else {
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/* Section. */
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phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
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*page_size = 0x100000;
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}
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ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
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xn = desc & (1 << 4);
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pxn = desc & 1;
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ns = extract32(desc, 19, 1);
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} else {
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if (cpu_isar_feature(aa32_pxn, cpu)) {
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pxn = (desc >> 2) & 1;
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}
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ns = extract32(desc, 3, 1);
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/* Lookup l2 entry. */
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table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
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desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
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mmu_idx, fi);
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if (fi->type != ARMFault_None) {
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goto do_fault;
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}
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ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
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switch (desc & 3) {
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case 0: /* Page translation fault. */
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fi->type = ARMFault_Translation;
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goto do_fault;
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case 1: /* 64k page. */
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phys_addr = (desc & 0xffff0000) | (address & 0xffff);
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xn = desc & (1 << 15);
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*page_size = 0x10000;
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break;
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case 2: case 3: /* 4k page. */
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phys_addr = (desc & 0xfffff000) | (address & 0xfff);
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xn = desc & 1;
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*page_size = 0x1000;
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break;
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default:
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/* Never happens, but compiler isn't smart enough to tell. */
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g_assert_not_reached();
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}
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}
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if (domain_prot == 3) {
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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} else {
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if (pxn && !regime_is_user(env, mmu_idx)) {
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xn = 1;
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}
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if (xn && access_type == MMU_INST_FETCH) {
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fi->type = ARMFault_Permission;
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goto do_fault;
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}
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if (arm_feature(env, ARM_FEATURE_V6K) &&
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(regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
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/* The simplified model uses AP[0] as an access control bit. */
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if ((ap & 1) == 0) {
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/* Access flag fault. */
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fi->type = ARMFault_AccessFlag;
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goto do_fault;
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}
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*prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
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} else {
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*prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
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}
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if (*prot && !xn) {
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*prot |= PAGE_EXEC;
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}
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if (!(*prot & (1 << access_type))) {
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/* Access permission fault. */
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fi->type = ARMFault_Permission;
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goto do_fault;
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}
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}
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if (ns) {
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/* The NS bit will (as required by the architecture) have no effect if
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* the CPU doesn't support TZ or this is a non-secure translation
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* regime, because the attribute will already be non-secure.
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*/
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attrs->secure = false;
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}
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*phys_ptr = phys_addr;
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return false;
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do_fault:
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fi->domain = domain;
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fi->level = level;
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return true;
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}
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/**
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* get_phys_addr - get the physical address for this virtual address
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*
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@ -25,15 +25,18 @@ bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
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uint32_t *table, uint32_t address);
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int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
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int ap, int domain_prot);
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int simple_ap_to_rw_prot_is_user(int ap, bool is_user);
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static inline int
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simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
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{
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return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
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}
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bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, int *prot,
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ARMMMUFaultInfo *fi);
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bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
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target_ulong *page_size, ARMMMUFaultInfo *fi);
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bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, int *prot,
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