tcg/tci: Inline tci_write_reg64 into 64-bit callers
Note that we had two functions of the same name: a 32-bit version which took two register numbers and a 64-bit version which was a no-op wrapper for tcg_write_reg. After this, we are left with only the 32-bit version. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
85bbbf7088
commit
5410e4347b
60
tcg/tci.c
60
tcg/tci.c
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@ -124,12 +124,6 @@ static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index,
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tci_write_reg(regs, low_index, value);
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tci_write_reg(regs, high_index, value >> 32);
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}
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#elif TCG_TARGET_REG_BITS == 64
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static void
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tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value)
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{
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tci_write_reg(regs, index, value);
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}
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#endif
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#if TCG_TARGET_REG_BITS == 32
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@ -559,7 +553,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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t1 = tci_read_r64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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condition = *tb_ptr++;
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tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition));
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tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
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break;
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#endif
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case INDEX_op_mov_i32:
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@ -839,12 +833,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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case INDEX_op_mov_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1);
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tci_write_reg(regs, t0, t1);
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break;
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case INDEX_op_tci_movi_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_i64(&tb_ptr);
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tci_write_reg64(regs, t0, t1);
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tci_write_reg(regs, t0, t1);
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break;
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/* Load/store operations (64 bit). */
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@ -886,7 +880,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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t0 = *tb_ptr++;
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t1 = tci_read_r(regs, &tb_ptr);
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t2 = tci_read_s32(&tb_ptr);
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tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2));
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tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
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break;
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case INDEX_op_st8_i64:
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t0 = tci_read_r8(regs, &tb_ptr);
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@ -920,19 +914,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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t0 = *tb_ptr++;
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t1 = tci_read_ri64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1 + t2);
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tci_write_reg(regs, t0, t1 + t2);
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break;
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case INDEX_op_sub_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_ri64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1 - t2);
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tci_write_reg(regs, t0, t1 - t2);
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break;
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case INDEX_op_mul_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_ri64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1 * t2);
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tci_write_reg(regs, t0, t1 * t2);
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break;
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#if TCG_TARGET_HAS_div_i64
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case INDEX_op_div_i64:
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@ -951,19 +945,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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t0 = *tb_ptr++;
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t1 = tci_read_ri64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1 & t2);
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tci_write_reg(regs, t0, t1 & t2);
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break;
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case INDEX_op_or_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_ri64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1 | t2);
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tci_write_reg(regs, t0, t1 | t2);
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break;
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case INDEX_op_xor_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_ri64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1 ^ t2);
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tci_write_reg(regs, t0, t1 ^ t2);
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break;
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/* Shift/rotate operations (64 bit). */
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@ -972,32 +966,32 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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t0 = *tb_ptr++;
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t1 = tci_read_ri64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1 << (t2 & 63));
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tci_write_reg(regs, t0, t1 << (t2 & 63));
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break;
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case INDEX_op_shr_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_ri64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1 >> (t2 & 63));
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tci_write_reg(regs, t0, t1 >> (t2 & 63));
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break;
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case INDEX_op_sar_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_ri64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63)));
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tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
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break;
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#if TCG_TARGET_HAS_rot_i64
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case INDEX_op_rotl_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_ri64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, rol64(t1, t2 & 63));
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tci_write_reg(regs, t0, rol64(t1, t2 & 63));
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break;
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case INDEX_op_rotr_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_ri64(regs, &tb_ptr);
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t2 = tci_read_ri64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, ror64(t1, t2 & 63));
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tci_write_reg(regs, t0, ror64(t1, t2 & 63));
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break;
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#endif
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#if TCG_TARGET_HAS_deposit_i64
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@ -1008,7 +1002,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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tmp16 = *tb_ptr++;
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tmp8 = *tb_ptr++;
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tmp64 = (((1ULL << tmp8) - 1) << tmp16);
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tci_write_reg64(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
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tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
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break;
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#endif
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case INDEX_op_brcond_i64:
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@ -1026,28 +1020,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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case INDEX_op_ext8u_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r8(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1);
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tci_write_reg(regs, t0, t1);
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break;
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#endif
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#if TCG_TARGET_HAS_ext8s_i64
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case INDEX_op_ext8s_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r8s(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1);
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tci_write_reg(regs, t0, t1);
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break;
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#endif
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#if TCG_TARGET_HAS_ext16s_i64
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case INDEX_op_ext16s_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r16s(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1);
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tci_write_reg(regs, t0, t1);
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break;
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#endif
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#if TCG_TARGET_HAS_ext16u_i64
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case INDEX_op_ext16u_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r16(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1);
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tci_write_reg(regs, t0, t1);
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break;
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#endif
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#if TCG_TARGET_HAS_ext32s_i64
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@ -1056,7 +1050,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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case INDEX_op_ext_i32_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r32s(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1);
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tci_write_reg(regs, t0, t1);
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break;
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#if TCG_TARGET_HAS_ext32u_i64
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case INDEX_op_ext32u_i64:
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@ -1064,41 +1058,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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case INDEX_op_extu_i32_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r32(regs, &tb_ptr);
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tci_write_reg64(regs, t0, t1);
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tci_write_reg(regs, t0, t1);
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break;
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#if TCG_TARGET_HAS_bswap16_i64
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case INDEX_op_bswap16_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r16(regs, &tb_ptr);
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tci_write_reg64(regs, t0, bswap16(t1));
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tci_write_reg(regs, t0, bswap16(t1));
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break;
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#endif
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#if TCG_TARGET_HAS_bswap32_i64
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case INDEX_op_bswap32_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r32(regs, &tb_ptr);
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tci_write_reg64(regs, t0, bswap32(t1));
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tci_write_reg(regs, t0, bswap32(t1));
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break;
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#endif
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#if TCG_TARGET_HAS_bswap64_i64
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case INDEX_op_bswap64_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, bswap64(t1));
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tci_write_reg(regs, t0, bswap64(t1));
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break;
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#endif
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#if TCG_TARGET_HAS_not_i64
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case INDEX_op_not_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, ~t1);
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tci_write_reg(regs, t0, ~t1);
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break;
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#endif
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#if TCG_TARGET_HAS_neg_i64
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case INDEX_op_neg_i64:
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t0 = *tb_ptr++;
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t1 = tci_read_r64(regs, &tb_ptr);
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tci_write_reg64(regs, t0, -t1);
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tci_write_reg(regs, t0, -t1);
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break;
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#endif
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#endif /* TCG_TARGET_REG_BITS == 64 */
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