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target/riscv: Update the CSRs to the v0.6 Hyp extension

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com
Message-Id: <4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis 2020-08-12 12:13:36 -07:00
parent f2d5850f71
commit 543ba53157
1 changed files with 8 additions and 6 deletions
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14
target/riscv/cpu_bits.h
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@ -437,15 +437,17 @@
#endif
/* hstatus CSR bits */
#define HSTATUS_SPRV 0x00000001
#define HSTATUS_VSBE 0x00000020
#define HSTATUS_GVA 0x00000040
#define HSTATUS_SPV 0x00000080
#define HSTATUS_SP2P 0x00000100
#define HSTATUS_SP2V 0x00000200
#define HSTATUS_SPVP 0x00000100
#define HSTATUS_HU 0x00000200
#define HSTATUS_VGEIN 0x0003F000
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
#define HSTATUS_HU 0x00000200
#define HSTATUS_GVA 0x00000040
#define HSTATUS_SPVP 0x00000100
#if defined(TARGET_RISCV64)
#define HSTATUS_VSXL 0x300000000
#endif
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL