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target/sparc: Move PREFETCH, PREFETCHA to decodetree

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Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-05 00:20:37 -07:00
parent d0a11d25f0
commit 5458fd3153
2 changed files with 14 additions and 17 deletions
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8
target/sparc/insns.decode
View File

@ -231,6 +231,9 @@ RESTORE 10 ..... 111101 ..... . ............. @r_r_ri
DONE 10 00000 111110 00000 0 0000000000000
RETRY 10 00001 111110 00000 0 0000000000000
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
##
## Major Opcode 11 -- load and store instructions
##
@ -299,8 +302,9 @@ CASA 11 ..... 111100 ..... . ............. @casa_imm
CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi
CASXA 11 ..... 111110 ..... . ............. @casa_imm
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH
NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH
NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA
NCP 11 ----- 110000 ----- --------- ----- # v8 LDC
NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR

23
target/sparc/translate.c
View File

@ -4031,17 +4031,12 @@ static bool trans_NOP(DisasContext *dc, arg_NOP *a)
return advance_pc(dc);
}
static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a)
{
/*
* TODO: Need a feature bit for sparcv8.
* In the meantime, treat all 32-bit cpus like sparcv7.
*/
if (avail_32(dc)) {
return advance_pc(dc);
}
return false;
}
/*
* TODO: Need a feature bit for sparcv8.
* In the meantime, treat all 32-bit cpus like sparcv7.
*/
TRANS(NOP_v7, 32, trans_NOP, a)
TRANS(NOP_v9, 64, trans_NOP, a)
static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op,
void (*func)(TCGv, TCGv, TCGv),
@ -5457,10 +5452,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x0b: /* V9 ldx */
case 0x18: /* V9 ldswa */
case 0x1b: /* V9 ldxa */
case 0x2d: /* V9 prefetch */
case 0x3d: /* V9 prefetcha */
goto illegal_insn; /* in decodetree */
#ifdef TARGET_SPARC64
case 0x2d: /* V9 prefetch, no effect */
goto skip_move;
case 0x30: /* V9 ldfa */
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
@ -5475,8 +5470,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
gen_update_fprs_dirty(dc, DFPREG(rd));
goto skip_move;
case 0x3d: /* V9 prefetcha, no effect */
goto skip_move;
case 0x32: /* V9 ldqfa */
CHECK_FPU_FEATURE(dc, FLOAT128);
if (gen_trap_ifnofpu(dc)) {