target-ppc: use the new rotr/rotri instructions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5608 c046a42c-6fe2-441c-8c8c-71466251a162
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158245714e
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54843a5861
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@ -1673,20 +1673,21 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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target_ulong mask;
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target_ulong mask;
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t0 = tcg_temp_new(TCG_TYPE_TL);
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t0 = tcg_temp_new(TCG_TYPE_TL);
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t1 = tcg_temp_new(TCG_TYPE_TL);
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#if defined(TARGET_PPC64)
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if (likely(sh == 0)) {
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t1 = tcg_temp_new(TCG_TYPE_I32);
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tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
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} else {
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tcg_gen_rotli_i32(t1, t1, sh);
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tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_extu_i32_i64(t0, t1);
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tcg_gen_shli_tl(t0, t1, sh);
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tcg_temp_free(t1);
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tcg_gen_shri_tl(t1, t1, 32 - sh);
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#else
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tcg_gen_or_tl(t0, t0, t1);
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tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
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}
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#endif
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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mb += 32;
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mb += 32;
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me += 32;
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me += 32;
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#endif
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#endif
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mask = MASK(mb, me);
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mask = MASK(mb, me);
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t1 = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_andi_tl(t0, t0, mask);
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tcg_gen_andi_tl(t0, t0, mask);
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tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
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tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
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tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
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tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
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@ -1723,16 +1724,15 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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tcg_temp_free(t0);
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tcg_temp_free(t0);
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} else {
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} else {
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TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
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TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
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if (likely(sh != 0)) {
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#if defined(TARGET_PPC64)
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TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
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TCGv t1 = tcg_temp_new(TCG_TYPE_I32);
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tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_shli_tl(t1, t0, sh);
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tcg_gen_rotli_i32(t1, t1, sh);
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tcg_gen_shri_tl(t0, t0, 32 - sh);
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tcg_gen_extu_i32_i64(t0, t1);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_temp_free(t1);
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tcg_temp_free(t1);
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#else
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} else {
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tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
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tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
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#endif
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}
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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mb += 32;
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mb += 32;
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me += 32;
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me += 32;
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@ -1747,31 +1747,37 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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{
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{
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uint32_t mb, me;
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uint32_t mb, me;
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TCGv t0, t1, t2;
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TCGv t0;
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#if defined(TARGET_PPC64)
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TCGv t1, t2;
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#endif
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mb = MB(ctx->opcode);
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mb = MB(ctx->opcode);
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me = ME(ctx->opcode);
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me = ME(ctx->opcode);
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t0 = tcg_temp_new(TCG_TYPE_TL);
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t0 = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
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tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
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t1 = tcg_temp_new(TCG_TYPE_TL);
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#if defined(TARGET_PPC64)
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tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
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t1 = tcg_temp_new(TCG_TYPE_I32);
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t2 = tcg_temp_new(TCG_TYPE_TL);
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t2 = tcg_temp_new(TCG_TYPE_I32);
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tcg_gen_shl_tl(t2, t1, t0);
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tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_subfi_tl(t0, 32, t0);
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tcg_gen_trunc_i64_i32(t2, t0);
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tcg_gen_shr_tl(t1, t1, t0);
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tcg_gen_rotl_i32(t1, t1, t2);
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tcg_temp_free(t0);
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tcg_gen_extu_i32_i64(t0, t1);
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tcg_gen_or_tl(t2, t2, t1);
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tcg_temp_free(t1);
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tcg_temp_free(t1);
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tcg_temp_free(t2);
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#else
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tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
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#endif
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if (unlikely(mb != 0 || me != 31)) {
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if (unlikely(mb != 0 || me != 31)) {
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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mb += 32;
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mb += 32;
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me += 32;
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me += 32;
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#endif
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#endif
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tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t2, MASK(mb, me));
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tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
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} else {
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} else {
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tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t2);
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
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}
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}
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tcg_temp_free(t2);
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tcg_temp_free(t0);
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if (unlikely(Rc(ctx->opcode) != 0))
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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}
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@ -1817,17 +1823,9 @@ static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
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tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
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tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
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} else {
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} else {
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TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
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TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
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if (likely(sh != 0)) {
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tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
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TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
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tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_temp_free(t1);
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} else {
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tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
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}
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if (likely(mb == 0 && me == 63)) {
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if (likely(mb == 0 && me == 63)) {
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tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
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} else {
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} else {
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tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
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tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
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}
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}
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@ -1870,23 +1868,19 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04);
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static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
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static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
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uint32_t me)
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uint32_t me)
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{
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{
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TCGv t0, t1;
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TCGv t0;
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mb = MB(ctx->opcode);
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mb = MB(ctx->opcode);
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me = ME(ctx->opcode);
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me = ME(ctx->opcode);
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t0 = tcg_temp_new(TCG_TYPE_TL);
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t0 = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
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tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
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t1 = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
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tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t0);
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tcg_gen_subfi_tl(t0, 64, t0);
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tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
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tcg_gen_or_tl(t1, t1, t0);
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tcg_temp_free(t0);
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if (unlikely(mb != 0 || me != 63)) {
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if (unlikely(mb != 0 || me != 63)) {
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tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t1, MASK(mb, me));
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tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
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} else
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} else {
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
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tcg_temp_free(t1);
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}
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tcg_temp_free(t0);
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if (unlikely(Rc(ctx->opcode) != 0))
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if (unlikely(Rc(ctx->opcode) != 0))
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
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}
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}
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@ -1924,14 +1918,8 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
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target_ulong mask;
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target_ulong mask;
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t0 = tcg_temp_new(TCG_TYPE_TL);
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t0 = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
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t1 = tcg_temp_new(TCG_TYPE_TL);
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t1 = tcg_temp_new(TCG_TYPE_TL);
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if (likely(sh == 0)) {
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tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
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} else {
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tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
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tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);
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tcg_gen_or_tl(t0, t0, t1);
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}
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mask = MASK(mb, me);
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mask = MASK(mb, me);
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tcg_gen_andi_tl(t0, t0, mask);
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tcg_gen_andi_tl(t0, t0, mask);
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tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
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tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
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