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target/arm: Conditionalize DBGDIDR

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Only define the register if it exists for the cpu.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210120031656.737646-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-01-28 12:00:10 +00:00 committed by Peter Maydell
parent 1d51bc96cc
commit 54a78718be
1 changed files with 15 additions and 6 deletions
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21
target/arm/helper.c
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@ -6567,11 +6567,21 @@ static void define_debug_regs(ARMCPU *cpu)
*/ */
int i; int i;
int wrps, brps, ctx_cmps; int wrps, brps, ctx_cmps;
ARMCPRegInfo dbgdidr = {
.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, /*
.access = PL0_R, .accessfn = access_tda, * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr, * use AArch32. Given that bit 15 is RES1, if the value is 0 then
}; * the register must not exist for this cpu.
*/
if (cpu->isar.dbgdidr != 0) {
ARMCPRegInfo dbgdidr = {
.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
.opc1 = 0, .opc2 = 0,
.access = PL0_R, .accessfn = access_tda,
.type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
};
define_one_arm_cp_reg(cpu, &dbgdidr);
}
/* Note that all these register fields hold "number of Xs minus 1". */ /* Note that all these register fields hold "number of Xs minus 1". */
brps = arm_num_brps(cpu); brps = arm_num_brps(cpu);
@ -6580,7 +6590,6 @@ static void define_debug_regs(ARMCPU *cpu)
assert(ctx_cmps <= brps); assert(ctx_cmps <= brps);
define_one_arm_cp_reg(cpu, &dbgdidr);
define_arm_cp_regs(cpu, debug_cp_reginfo); define_arm_cp_regs(cpu, debug_cp_reginfo);
if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {