target/m68k: Drop mark_to_release
Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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34aac056a4
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54dc8d2f91
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@ -121,35 +121,9 @@ typedef struct DisasContext {
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int done_mac;
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int done_mac;
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int writeback_mask;
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int writeback_mask;
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TCGv writeback[8];
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TCGv writeback[8];
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#define MAX_TO_RELEASE 8
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int release_count;
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TCGv release[MAX_TO_RELEASE];
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bool ss_active;
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bool ss_active;
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} DisasContext;
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} DisasContext;
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static void init_release_array(DisasContext *s)
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{
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#ifdef CONFIG_DEBUG_TCG
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memset(s->release, 0, sizeof(s->release));
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#endif
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s->release_count = 0;
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}
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static void do_release(DisasContext *s)
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{
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int i;
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for (i = 0; i < s->release_count; i++) {
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tcg_temp_free(s->release[i]);
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}
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init_release_array(s);
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}
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static TCGv mark_to_release(DisasContext *s, TCGv tmp)
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{
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g_assert(s->release_count < MAX_TO_RELEASE);
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return s->release[s->release_count++] = tmp;
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}
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static TCGv get_areg(DisasContext *s, unsigned regno)
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static TCGv get_areg(DisasContext *s, unsigned regno)
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{
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{
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if (s->writeback_mask & (1 << regno)) {
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if (s->writeback_mask & (1 << regno)) {
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@ -396,8 +370,7 @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
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gen_store(s, opsize, addr, val, index);
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gen_store(s, opsize, addr, val, index);
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return store_dummy;
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return store_dummy;
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} else {
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} else {
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return mark_to_release(s, gen_load(s, opsize, addr,
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return gen_load(s, opsize, addr, what == EA_LOADS, index);
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what == EA_LOADS, index));
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}
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}
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}
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}
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@ -491,7 +464,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
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} else {
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} else {
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bd = 0;
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bd = 0;
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}
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}
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tmp = mark_to_release(s, tcg_temp_new());
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tmp = tcg_temp_new();
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if ((ext & 0x44) == 0) {
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if ((ext & 0x44) == 0) {
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/* pre-index */
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/* pre-index */
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add = gen_addr_index(s, ext, tmp);
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add = gen_addr_index(s, ext, tmp);
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@ -501,7 +474,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
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if ((ext & 0x80) == 0) {
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if ((ext & 0x80) == 0) {
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/* base not suppressed */
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/* base not suppressed */
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if (IS_NULL_QREG(base)) {
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if (IS_NULL_QREG(base)) {
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base = mark_to_release(s, tcg_const_i32(offset + bd));
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base = tcg_const_i32(offset + bd);
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bd = 0;
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bd = 0;
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}
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}
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if (!IS_NULL_QREG(add)) {
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if (!IS_NULL_QREG(add)) {
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@ -517,11 +490,11 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
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add = tmp;
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add = tmp;
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}
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}
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} else {
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} else {
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add = mark_to_release(s, tcg_const_i32(bd));
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add = tcg_const_i32(bd);
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}
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}
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if ((ext & 3) != 0) {
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if ((ext & 3) != 0) {
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/* memory indirect */
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/* memory indirect */
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base = mark_to_release(s, gen_load(s, OS_LONG, add, 0, IS_USER(s)));
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base = gen_load(s, OS_LONG, add, 0, IS_USER(s));
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if ((ext & 0x44) == 4) {
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if ((ext & 0x44) == 4) {
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add = gen_addr_index(s, ext, tmp);
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add = gen_addr_index(s, ext, tmp);
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tcg_gen_add_i32(tmp, add, base);
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tcg_gen_add_i32(tmp, add, base);
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@ -546,7 +519,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
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}
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}
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} else {
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} else {
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/* brief extension word format */
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/* brief extension word format */
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tmp = mark_to_release(s, tcg_temp_new());
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tmp = tcg_temp_new();
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add = gen_addr_index(s, ext, tmp);
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add = gen_addr_index(s, ext, tmp);
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if (!IS_NULL_QREG(base)) {
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if (!IS_NULL_QREG(base)) {
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tcg_gen_add_i32(tmp, add, base);
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tcg_gen_add_i32(tmp, add, base);
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@ -676,7 +649,7 @@ static inline TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int sign)
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if (opsize == OS_LONG) {
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if (opsize == OS_LONG) {
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tmp = val;
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tmp = val;
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} else {
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} else {
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tmp = mark_to_release(s, tcg_temp_new());
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tmp = tcg_temp_new();
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gen_ext(tmp, val, opsize, sign);
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gen_ext(tmp, val, opsize, sign);
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}
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}
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@ -802,7 +775,7 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
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return NULL_QREG;
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return NULL_QREG;
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}
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}
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reg = get_areg(s, reg0);
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reg = get_areg(s, reg0);
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tmp = mark_to_release(s, tcg_temp_new());
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tmp = tcg_temp_new();
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if (reg0 == 7 && opsize == OS_BYTE &&
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if (reg0 == 7 && opsize == OS_BYTE &&
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m68k_feature(s->env, M68K_FEATURE_M68K)) {
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m68k_feature(s->env, M68K_FEATURE_M68K)) {
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tcg_gen_subi_i32(tmp, reg, 2);
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tcg_gen_subi_i32(tmp, reg, 2);
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@ -812,7 +785,7 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
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return tmp;
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return tmp;
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case 5: /* Indirect displacement. */
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case 5: /* Indirect displacement. */
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reg = get_areg(s, reg0);
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reg = get_areg(s, reg0);
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tmp = mark_to_release(s, tcg_temp_new());
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tmp = tcg_temp_new();
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ext = read_im16(env, s);
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ext = read_im16(env, s);
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tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
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tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
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return tmp;
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return tmp;
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@ -823,14 +796,14 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
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switch (reg0) {
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switch (reg0) {
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case 0: /* Absolute short. */
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case 0: /* Absolute short. */
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offset = (int16_t)read_im16(env, s);
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offset = (int16_t)read_im16(env, s);
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return mark_to_release(s, tcg_const_i32(offset));
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return tcg_const_i32(offset);
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case 1: /* Absolute long. */
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case 1: /* Absolute long. */
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offset = read_im32(env, s);
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offset = read_im32(env, s);
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return mark_to_release(s, tcg_const_i32(offset));
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return tcg_const_i32(offset);
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case 2: /* pc displacement */
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case 2: /* pc displacement */
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offset = s->pc;
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offset = s->pc;
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offset += (int16_t)read_im16(env, s);
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offset += (int16_t)read_im16(env, s);
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return mark_to_release(s, tcg_const_i32(offset));
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return tcg_const_i32(offset);
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case 3: /* pc index+displacement. */
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case 3: /* pc index+displacement. */
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return gen_lea_indexed(env, s, NULL_QREG);
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return gen_lea_indexed(env, s, NULL_QREG);
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case 4: /* Immediate. */
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case 4: /* Immediate. */
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@ -958,7 +931,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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}
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}
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return mark_to_release(s, tcg_const_i32(offset));
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return tcg_const_i32(offset);
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default:
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default:
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return NULL_QREG;
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return NULL_QREG;
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}
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}
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@ -6287,7 +6260,6 @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
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dc->cc_op_synced = 1;
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dc->cc_op_synced = 1;
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dc->done_mac = 0;
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dc->done_mac = 0;
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dc->writeback_mask = 0;
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dc->writeback_mask = 0;
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init_release_array(dc);
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dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
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dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
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/* If architectural single step active, limit to 1 */
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/* If architectural single step active, limit to 1 */
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@ -6314,7 +6286,6 @@ static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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opcode_table[insn](env, dc, insn);
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opcode_table[insn](env, dc, insn);
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do_writebacks(dc);
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do_writebacks(dc);
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do_release(dc);
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dc->pc_prev = dc->base.pc_next;
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dc->pc_prev = dc->base.pc_next;
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dc->base.pc_next = dc->pc;
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dc->base.pc_next = dc->pc;
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