OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

sh4: Coding style: Remove tabs

Browse Source 
Replaces TABS with spaces to ensure have a consistent coding
style with an indentation of 4 spaces in the SH4 subsystem.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/376
Signed-off-by: Yihuan Pan <xun794@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20231124044554.513752-1-xun794@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Yihuan Pan 2023-11-24 12:45:54 +08:00 committed by Thomas Huth
parent 5689d4bda6
commit 5533936127
5 changed files with 1027 additions and 1027 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

204
linux-user/sh4/termbits.h
View File

@ -39,86 +39,86 @@ struct target_termios {
#define TARGET_VEOL2 16 #define TARGET_VEOL2 16
/* c_iflag bits */ /* c_iflag bits */
#define TARGET_IGNBRK 0000001 #define TARGET_IGNBRK 0000001
#define TARGET_BRKINT 0000002 #define TARGET_BRKINT 0000002
#define TARGET_IGNPAR 0000004 #define TARGET_IGNPAR 0000004
#define TARGET_PARMRK 0000010 #define TARGET_PARMRK 0000010
#define TARGET_INPCK 0000020 #define TARGET_INPCK 0000020
#define TARGET_ISTRIP 0000040 #define TARGET_ISTRIP 0000040
#define TARGET_INLCR 0000100 #define TARGET_INLCR 0000100
#define TARGET_IGNCR 0000200 #define TARGET_IGNCR 0000200
#define TARGET_ICRNL 0000400 #define TARGET_ICRNL 0000400
#define TARGET_IUCLC 0001000 #define TARGET_IUCLC 0001000
#define TARGET_IXON 0002000 #define TARGET_IXON 0002000
#define TARGET_IXANY 0004000 #define TARGET_IXANY 0004000
#define TARGET_IXOFF 0010000 #define TARGET_IXOFF 0010000
#define TARGET_IMAXBEL 0020000 #define TARGET_IMAXBEL 0020000
#define TARGET_IUTF8 0040000 #define TARGET_IUTF8 0040000
/* c_oflag bits */ /* c_oflag bits */
#define TARGET_OPOST 0000001 #define TARGET_OPOST 0000001
#define TARGET_OLCUC 0000002 #define TARGET_OLCUC 0000002
#define TARGET_ONLCR 0000004 #define TARGET_ONLCR 0000004
#define TARGET_OCRNL 0000010 #define TARGET_OCRNL 0000010
#define TARGET_ONOCR 0000020 #define TARGET_ONOCR 0000020
#define TARGET_ONLRET 0000040 #define TARGET_ONLRET 0000040
#define TARGET_OFILL 0000100 #define TARGET_OFILL 0000100
#define TARGET_OFDEL 0000200 #define TARGET_OFDEL 0000200
#define TARGET_NLDLY 0000400 #define TARGET_NLDLY 0000400
#define TARGET_NL0 0000000 #define TARGET_NL0 0000000
#define TARGET_NL1 0000400 #define TARGET_NL1 0000400
#define TARGET_CRDLY 0003000 #define TARGET_CRDLY 0003000
#define TARGET_CR0 0000000 #define TARGET_CR0 0000000
#define TARGET_CR1 0001000 #define TARGET_CR1 0001000
#define TARGET_CR2 0002000 #define TARGET_CR2 0002000
#define TARGET_CR3 0003000 #define TARGET_CR3 0003000
#define TARGET_TABDLY 0014000 #define TARGET_TABDLY 0014000
#define TARGET_TAB0 0000000 #define TARGET_TAB0 0000000
#define TARGET_TAB1 0004000 #define TARGET_TAB1 0004000
#define TARGET_TAB2 0010000 #define TARGET_TAB2 0010000
#define TARGET_TAB3 0014000 #define TARGET_TAB3 0014000
#define TARGET_XTABS 0014000 #define TARGET_XTABS 0014000
#define TARGET_BSDLY 0020000 #define TARGET_BSDLY 0020000
#define TARGET_BS0 0000000 #define TARGET_BS0 0000000
#define TARGET_BS1 0020000 #define TARGET_BS1 0020000
#define TARGET_VTDLY 0040000 #define TARGET_VTDLY 0040000
#define TARGET_VT0 0000000 #define TARGET_VT0 0000000
#define TARGET_VT1 0040000 #define TARGET_VT1 0040000
#define TARGET_FFDLY 0100000 #define TARGET_FFDLY 0100000
#define TARGET_FF0 0000000 #define TARGET_FF0 0000000
#define TARGET_FF1 0100000 #define TARGET_FF1 0100000
/* c_cflag bit meaning */ /* c_cflag bit meaning */
#define TARGET_CBAUD 0010017 #define TARGET_CBAUD 0010017
#define TARGET_B0 0000000 /* hang up */ #define TARGET_B0 0000000 /* hang up */
#define TARGET_B50 0000001 #define TARGET_B50 0000001
#define TARGET_B75 0000002 #define TARGET_B75 0000002
#define TARGET_B110 0000003 #define TARGET_B110 0000003
#define TARGET_B134 0000004 #define TARGET_B134 0000004
#define TARGET_B150 0000005 #define TARGET_B150 0000005
#define TARGET_B200 0000006 #define TARGET_B200 0000006
#define TARGET_B300 0000007 #define TARGET_B300 0000007
#define TARGET_B600 0000010 #define TARGET_B600 0000010
#define TARGET_B1200 0000011 #define TARGET_B1200 0000011
#define TARGET_B1800 0000012 #define TARGET_B1800 0000012
#define TARGET_B2400 0000013 #define TARGET_B2400 0000013
#define TARGET_B4800 0000014 #define TARGET_B4800 0000014
#define TARGET_B9600 0000015 #define TARGET_B9600 0000015
#define TARGET_B19200 0000016 #define TARGET_B19200 0000016
#define TARGET_B38400 0000017 #define TARGET_B38400 0000017
#define TARGET_EXTA B19200 #define TARGET_EXTA B19200
#define TARGET_EXTB B38400 #define TARGET_EXTB B38400
#define TARGET_CSIZE 0000060 #define TARGET_CSIZE 0000060
#define TARGET_CS5 0000000 #define TARGET_CS5 0000000
#define TARGET_CS6 0000020 #define TARGET_CS6 0000020
#define TARGET_CS7 0000040 #define TARGET_CS7 0000040
#define TARGET_CS8 0000060 #define TARGET_CS8 0000060
#define TARGET_CSTOPB 0000100 #define TARGET_CSTOPB 0000100
#define TARGET_CREAD 0000200 #define TARGET_CREAD 0000200
#define TARGET_PARENB 0000400 #define TARGET_PARENB 0000400
#define TARGET_PARODD 0001000 #define TARGET_PARODD 0001000
#define TARGET_HUPCL 0002000 #define TARGET_HUPCL 0002000
#define TARGET_CLOCAL 0004000 #define TARGET_CLOCAL 0004000
#define TARGET_CBAUDEX 0010000 #define TARGET_CBAUDEX 0010000
#define TARGET_B57600 0010001 #define TARGET_B57600 0010001
#define TARGET_B115200 0010002 #define TARGET_B115200 0010002
@ -135,44 +135,44 @@ struct target_termios {
#define TARGET_B3000000 0010015 #define TARGET_B3000000 0010015
#define TARGET_B3500000 0010016 #define TARGET_B3500000 0010016
#define TARGET_B4000000 0010017 #define TARGET_B4000000 0010017
#define TARGET_CIBAUD 002003600000 /* input baud rate (not used) */ #define TARGET_CIBAUD 002003600000 /* input baud rate (not used) */
#define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */ #define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */
#define TARGET_CRTSCTS 020000000000 /* flow control */ #define TARGET_CRTSCTS 020000000000 /* flow control */
/* c_lflag bits */ /* c_lflag bits */
#define TARGET_ISIG 0000001 #define TARGET_ISIG 0000001
#define TARGET_ICANON 0000002 #define TARGET_ICANON 0000002
#define TARGET_XCASE 0000004 #define TARGET_XCASE 0000004
#define TARGET_ECHO 0000010 #define TARGET_ECHO 0000010
#define TARGET_ECHOE 0000020 #define TARGET_ECHOE 0000020
#define TARGET_ECHOK 0000040 #define TARGET_ECHOK 0000040
#define TARGET_ECHONL 0000100 #define TARGET_ECHONL 0000100
#define TARGET_NOFLSH 0000200 #define TARGET_NOFLSH 0000200
#define TARGET_TOSTOP 0000400 #define TARGET_TOSTOP 0000400
#define TARGET_ECHOCTL 0001000 #define TARGET_ECHOCTL 0001000
#define TARGET_ECHOPRT 0002000 #define TARGET_ECHOPRT 0002000
#define TARGET_ECHOKE 0004000 #define TARGET_ECHOKE 0004000
#define TARGET_FLUSHO 0010000 #define TARGET_FLUSHO 0010000
#define TARGET_PENDIN 0040000 #define TARGET_PENDIN 0040000
#define TARGET_IEXTEN 0100000 #define TARGET_IEXTEN 0100000
#define TARGET_EXTPROC 0200000 #define TARGET_EXTPROC 0200000
/* tcflow() and TCXONC use these */ /* tcflow() and TCXONC use these */
#define TARGET_TCOOFF 0 #define TARGET_TCOOFF 0
#define TARGET_TCOON 1 #define TARGET_TCOON 1
#define TARGET_TCIOFF 2 #define TARGET_TCIOFF 2
#define TARGET_TCION 3 #define TARGET_TCION 3
/* tcflush() and TCFLSH use these */ /* tcflush() and TCFLSH use these */
#define TARGET_TCIFLUSH 0 #define TARGET_TCIFLUSH 0
#define TARGET_TCOFLUSH 1 #define TARGET_TCOFLUSH 1
#define TARGET_TCIOFLUSH 2 #define TARGET_TCIOFLUSH 2
/* tcsetattr uses these */ /* tcsetattr uses these */
#define TARGET_TCSANOW 0 #define TARGET_TCSANOW 0
#define TARGET_TCSADRAIN 1 #define TARGET_TCSADRAIN 1
#define TARGET_TARGET_TCSAFLUSH 2 #define TARGET_TARGET_TCSAFLUSH 2
/* ioctl */ /* ioctl */
#define TARGET_FIOCLEX TARGET_IO('f', 1) #define TARGET_FIOCLEX TARGET_IO('f', 1)

80
target/sh4/cpu.h
View File

@ -107,19 +107,19 @@
TB_FLAG_GUSA_MASK) TB_FLAG_GUSA_MASK)
typedef struct tlb_t { typedef struct tlb_t {
uint32_t vpn; /* virtual page number */ uint32_t vpn; /* virtual page number */
uint32_t ppn; /* physical page number */ uint32_t ppn; /* physical page number */
uint32_t size; /* mapped page size in bytes */ uint32_t size; /* mapped page size in bytes */
uint8_t asid; /* address space identifier */ uint8_t asid; /* address space identifier */
uint8_t v:1; /* validity */ uint8_t v:1; /* validity */
uint8_t sz:2; /* page size */ uint8_t sz:2; /* page size */
uint8_t sh:1; /* share status */ uint8_t sh:1; /* share status */
uint8_t c:1; /* cacheability */ uint8_t c:1; /* cacheability */
uint8_t pr:2; /* protection key */ uint8_t pr:2; /* protection key */
uint8_t d:1; /* dirty */ uint8_t d:1; /* dirty */
uint8_t wt:1; /* write through */ uint8_t wt:1; /* write through */
uint8_t sa:3; /* space attribute (PCMCIA) */ uint8_t sa:3; /* space attribute (PCMCIA) */
uint8_t tc:1; /* timing control */ uint8_t tc:1; /* timing control */
} tlb_t; } tlb_t;
#define UTLB_SIZE 64 #define UTLB_SIZE 64
@ -139,44 +139,44 @@ typedef struct memory_content {
} memory_content; } memory_content;
typedef struct CPUArchState { typedef struct CPUArchState {
uint32_t flags; /* general execution flags */ uint32_t flags; /* general execution flags */
uint32_t gregs[24]; /* general registers */ uint32_t gregs[24]; /* general registers */
float32 fregs[32]; /* floating point registers */ float32 fregs[32]; /* floating point registers */
uint32_t sr; /* status register (with T split out) */ uint32_t sr; /* status register (with T split out) */
uint32_t sr_m; /* M bit of status register */ uint32_t sr_m; /* M bit of status register */
uint32_t sr_q; /* Q bit of status register */ uint32_t sr_q; /* Q bit of status register */
uint32_t sr_t; /* T bit of status register */ uint32_t sr_t; /* T bit of status register */
uint32_t ssr; /* saved status register */ uint32_t ssr; /* saved status register */
uint32_t spc; /* saved program counter */ uint32_t spc; /* saved program counter */
uint32_t gbr; /* global base register */ uint32_t gbr; /* global base register */
uint32_t vbr; /* vector base register */ uint32_t vbr; /* vector base register */
uint32_t sgr; /* saved global register 15 */ uint32_t sgr; /* saved global register 15 */
uint32_t dbr; /* debug base register */ uint32_t dbr; /* debug base register */
uint32_t pc; /* program counter */ uint32_t pc; /* program counter */
uint32_t delayed_pc; /* target of delayed branch */ uint32_t delayed_pc; /* target of delayed branch */
uint32_t delayed_cond; /* condition of delayed branch */ uint32_t delayed_cond; /* condition of delayed branch */
uint32_t mach; /* multiply and accumulate high */ uint32_t mach; /* multiply and accumulate high */
uint32_t macl; /* multiply and accumulate low */ uint32_t macl; /* multiply and accumulate low */
uint32_t pr; /* procedure register */ uint32_t pr; /* procedure register */
uint32_t fpscr; /* floating point status/control register */ uint32_t fpscr; /* floating point status/control register */
uint32_t fpul; /* floating point communication register */ uint32_t fpul; /* floating point communication register */
/* float point status register */ /* float point status register */
float_status fp_status; float_status fp_status;
/* Those belong to the specific unit (SH7750) but are handled here */ /* Those belong to the specific unit (SH7750) but are handled here */
uint32_t mmucr; /* MMU control register */ uint32_t mmucr; /* MMU control register */
uint32_t pteh; /* page table entry high register */ uint32_t pteh; /* page table entry high register */
uint32_t ptel; /* page table entry low register */ uint32_t ptel; /* page table entry low register */
uint32_t ptea; /* page table entry assistance register */ uint32_t ptea; /* page table entry assistance register */
uint32_t ttb; /* translation table base register */ uint32_t ttb; /* translation table base register */
uint32_t tea; /* TLB exception address register */ uint32_t tea; /* TLB exception address register */
uint32_t tra; /* TRAPA exception register */ uint32_t tra; /* TRAPA exception register */
uint32_t expevt; /* exception event register */ uint32_t expevt; /* exception event register */
uint32_t intevt; /* interrupt event register */ uint32_t intevt; /* interrupt event register */
tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
tlb_t utlb[UTLB_SIZE]; /* unified translation table */ tlb_t utlb[UTLB_SIZE]; /* unified translation table */
/* LDST = LOCK_ADDR != -1. */ /* LDST = LOCK_ADDR != -1. */
uint32_t lock_addr; uint32_t lock_addr;
@ -186,13 +186,13 @@ typedef struct CPUArchState {
struct {} end_reset_fields; struct {} end_reset_fields;
/* Fields from here on are preserved over CPU reset. */ /* Fields from here on are preserved over CPU reset. */
int id; /* CPU model */ int id; /* CPU model */
/* The features that we should emulate. See sh_features above. */ /* The features that we should emulate. See sh_features above. */
uint32_t features; uint32_t features;
void *intc_handle; void *intc_handle;
int in_sleep; /* SR_BL ignored during sleep */ int in_sleep; /* SR_BL ignored during sleep */
memory_content *movcal_backup; memory_content *movcal_backup;
memory_content **movcal_backup_tail; memory_content **movcal_backup_tail;
} CPUSH4State; } CPUSH4State;

234
target/sh4/helper.c
View File

@ -84,60 +84,60 @@ void superh_cpu_do_interrupt(CPUState *cs)
if (do_irq) { if (do_irq) {
irq_vector = sh_intc_get_pending_vector(env->intc_handle, irq_vector = sh_intc_get_pending_vector(env->intc_handle,
(env->sr >> 4) & 0xf); (env->sr >> 4) & 0xf);
if (irq_vector == -1) { if (irq_vector == -1) {
return; /* masked */ return; /* masked */
} }
} }
if (qemu_loglevel_mask(CPU_LOG_INT)) { if (qemu_loglevel_mask(CPU_LOG_INT)) {
const char *expname; const char *expname;
switch (cs->exception_index) { switch (cs->exception_index) {
case 0x0e0: case 0x0e0:
expname = "addr_error"; expname = "addr_error";
break; break;
case 0x040: case 0x040:
expname = "tlb_miss"; expname = "tlb_miss";
break; break;
case 0x0a0: case 0x0a0:
expname = "tlb_violation"; expname = "tlb_violation";
break; break;
case 0x180: case 0x180:
expname = "illegal_instruction"; expname = "illegal_instruction";
break; break;
case 0x1a0: case 0x1a0:
expname = "slot_illegal_instruction"; expname = "slot_illegal_instruction";
break; break;
case 0x800: case 0x800:
expname = "fpu_disable"; expname = "fpu_disable";
break; break;
case 0x820: case 0x820:
expname = "slot_fpu"; expname = "slot_fpu";
break; break;
case 0x100: case 0x100:
expname = "data_write"; expname = "data_write";
break; break;
case 0x060: case 0x060:
expname = "dtlb_miss_write"; expname = "dtlb_miss_write";
break; break;
case 0x0c0: case 0x0c0:
expname = "dtlb_violation_write"; expname = "dtlb_violation_write";
break; break;
case 0x120: case 0x120:
expname = "fpu_exception"; expname = "fpu_exception";
break; break;
case 0x080: case 0x080:
expname = "initial_page_write"; expname = "initial_page_write";
break; break;
case 0x160: case 0x160:
expname = "trapa"; expname = "trapa";
break; break;
default: default:
expname = do_irq ? "interrupt" : "???"; expname = do_irq ? "interrupt" : "???";
break; break;
} }
qemu_log("exception 0x%03x [%s] raised\n", qemu_log("exception 0x%03x [%s] raised\n",
irq_vector, expname); irq_vector, expname);
log_cpu_state(cs, 0); log_cpu_state(cs, 0);
} }
@ -149,8 +149,8 @@ void superh_cpu_do_interrupt(CPUState *cs)
if (env->flags & TB_FLAG_DELAY_SLOT_MASK) { if (env->flags & TB_FLAG_DELAY_SLOT_MASK) {
/* Branch instruction should be executed again before delay slot. */ /* Branch instruction should be executed again before delay slot. */
env->spc -= 2; env->spc -= 2;
/* Clear flags for exception/interrupt routine. */ /* Clear flags for exception/interrupt routine. */
env->flags &= ~TB_FLAG_DELAY_SLOT_MASK; env->flags &= ~TB_FLAG_DELAY_SLOT_MASK;
} }
@ -191,19 +191,19 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb)
switch (itlbnb) { switch (itlbnb) {
case 0: case 0:
and_mask = 0x1f; and_mask = 0x1f;
break; break;
case 1: case 1:
and_mask = 0xe7; and_mask = 0xe7;
or_mask = 0x80; or_mask = 0x80;
break; break;
case 2: case 2:
and_mask = 0xfb; and_mask = 0xfb;
or_mask = 0x50; or_mask = 0x50;
break; break;
case 3: case 3:
or_mask = 0x2c; or_mask = 0x2c;
break; break;
} }
env->mmucr &= (and_mask << 24) | 0x00ffffff; env->mmucr &= (and_mask << 24) | 0x00ffffff;
@ -213,16 +213,16 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb)
static int itlb_replacement(CPUSH4State * env) static int itlb_replacement(CPUSH4State * env)
{ {
if ((env->mmucr & 0xe0000000) == 0xe0000000) { if ((env->mmucr & 0xe0000000) == 0xe0000000) {
return 0; return 0;
} }
if ((env->mmucr & 0x98000000) == 0x18000000) { if ((env->mmucr & 0x98000000) == 0x18000000) {
return 1; return 1;
} }
if ((env->mmucr & 0x54000000) == 0x04000000) { if ((env->mmucr & 0x54000000) == 0x04000000) {
return 2; return 2;
} }
if ((env->mmucr & 0x2c000000) == 0x00000000) { if ((env->mmucr & 0x2c000000) == 0x00000000) {
return 3; return 3;
} }
cpu_abort(env_cpu(env), "Unhandled itlb_replacement"); cpu_abort(env_cpu(env), "Unhandled itlb_replacement");
} }
@ -231,7 +231,7 @@ static int itlb_replacement(CPUSH4State * env)
Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/ */
static int find_tlb_entry(CPUSH4State * env, target_ulong address, static int find_tlb_entry(CPUSH4State * env, target_ulong address,
tlb_t * entries, uint8_t nbtlb, int use_asid) tlb_t * entries, uint8_t nbtlb, int use_asid)
{ {
int match = MMU_DTLB_MISS; int match = MMU_DTLB_MISS;
uint32_t start, end; uint32_t start, end;
@ -241,17 +241,17 @@ static int find_tlb_entry(CPUSH4State * env, target_ulong address,
asid = env->pteh & 0xff; asid = env->pteh & 0xff;
for (i = 0; i < nbtlb; i++) { for (i = 0; i < nbtlb; i++) {
if (!entries[i].v) if (!entries[i].v)
continue; /* Invalid entry */ continue; /* Invalid entry */
if (!entries[i].sh && use_asid && entries[i].asid != asid) if (!entries[i].sh && use_asid && entries[i].asid != asid)
continue; /* Bad ASID */ continue; /* Bad ASID */
start = (entries[i].vpn << 10) & ~(entries[i].size - 1); start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
end = start + entries[i].size - 1; end = start + entries[i].size - 1;
if (address >= start && address <= end) { /* Match */ if (address >= start && address <= end) { /* Match */
if (match != MMU_DTLB_MISS) if (match != MMU_DTLB_MISS)
return MMU_DTLB_MULTIPLE; /* Multiple match */ return MMU_DTLB_MULTIPLE; /* Multiple match */
match = i; match = i;
} }
} }
return match; return match;
} }
@ -265,7 +265,7 @@ static void increment_urc(CPUSH4State * env)
urc = ((env->mmucr) >> 10) & 0x3f; urc = ((env->mmucr) >> 10) & 0x3f;
urc++; urc++;
if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1)) if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
urc = 0; urc = 0;
env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
} }
@ -297,11 +297,11 @@ static int find_itlb_entry(CPUSH4State * env, target_ulong address,
e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
if (e == MMU_DTLB_MULTIPLE) { if (e == MMU_DTLB_MULTIPLE) {
e = MMU_ITLB_MULTIPLE; e = MMU_ITLB_MULTIPLE;
} else if (e == MMU_DTLB_MISS) { } else if (e == MMU_DTLB_MISS) {
e = MMU_ITLB_MISS; e = MMU_ITLB_MISS;
} else if (e >= 0) { } else if (e >= 0) {
update_itlb_use(env, e); update_itlb_use(env, e);
} }
return e; return e;
} }
@ -518,7 +518,7 @@ uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
} }
void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
uint32_t mem_value) uint32_t mem_value)
{ {
uint32_t vpn = (mem_value & 0xfffffc00) >> 10; uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
@ -601,7 +601,7 @@ uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
} }
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
uint32_t mem_value) uint32_t mem_value)
{ {
int associate = addr & 0x0000080; int associate = addr & 0x0000080;
uint32_t vpn = (mem_value & 0xfffffc00) >> 10; uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
@ -612,48 +612,48 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
if (associate) { if (associate) {
int i; int i;
tlb_t * utlb_match_entry = NULL; tlb_t * utlb_match_entry = NULL;
int needs_tlb_flush = 0; int needs_tlb_flush = 0;
/* search UTLB */ /* search UTLB */
for (i = 0; i < UTLB_SIZE; i++) { for (i = 0; i < UTLB_SIZE; i++) {
tlb_t * entry = &s->utlb[i]; tlb_t * entry = &s->utlb[i];
if (!entry->v) if (!entry->v)
continue; continue;
if (entry->vpn == vpn if (entry->vpn == vpn
&& (!use_asid || entry->asid == asid || entry->sh)) { && (!use_asid || entry->asid == asid || entry->sh)) {
if (utlb_match_entry) { if (utlb_match_entry) {
CPUState *cs = env_cpu(s); CPUState *cs = env_cpu(s);
/* Multiple TLB Exception */ /* Multiple TLB Exception */
cs->exception_index = 0x140; cs->exception_index = 0x140;
s->tea = addr; s->tea = addr;
break; break;
} }
if (entry->v && !v) if (entry->v && !v)
needs_tlb_flush = 1; needs_tlb_flush = 1;
entry->v = v; entry->v = v;
entry->d = d; entry->d = d;
utlb_match_entry = entry; utlb_match_entry = entry;
} }
increment_urc(s); /* per utlb access */ increment_urc(s); /* per utlb access */
} }
/* search ITLB */ /* search ITLB */
for (i = 0; i < ITLB_SIZE; i++) { for (i = 0; i < ITLB_SIZE; i++) {
tlb_t * entry = &s->itlb[i]; tlb_t * entry = &s->itlb[i];
if (entry->vpn == vpn if (entry->vpn == vpn
&& (!use_asid || entry->asid == asid || entry->sh)) { && (!use_asid || entry->asid == asid || entry->sh)) {
if (entry->v && !v) if (entry->v && !v)
needs_tlb_flush = 1; needs_tlb_flush = 1;
if (utlb_match_entry) if (utlb_match_entry)
*entry = *utlb_match_entry; *entry = *utlb_match_entry;
else else
entry->v = v; entry->v = v;
break; break;
} }
} }
if (needs_tlb_flush) { if (needs_tlb_flush) {
tlb_flush_page(env_cpu(s), vpn << 10); tlb_flush_page(env_cpu(s), vpn << 10);
@ -661,18 +661,18 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
} else { } else {
int index = (addr & 0x00003f00) >> 8; int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index]; tlb_t * entry = &s->utlb[index];
if (entry->v) { if (entry->v) {
CPUState *cs = env_cpu(s); CPUState *cs = env_cpu(s);
/* Overwriting valid entry in utlb. */ /* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10; target_ulong address = entry->vpn << 10;
tlb_flush_page(cs, address); tlb_flush_page(cs, address);
} }
entry->asid = asid; entry->asid = asid;
entry->vpn = vpn; entry->vpn = vpn;
entry->d = d; entry->d = d;
entry->v = v; entry->v = v;
increment_urc(s); increment_urc(s);
} }
} }

70
target/sh4/op_helper.c
View File

@ -114,12 +114,12 @@ void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
{ {
memory_content *r = g_new(memory_content, 1); memory_content *r = g_new(memory_content, 1);
r->address = address; r->address = address;
r->value = value; r->value = value;
r->next = NULL; r->next = NULL;
*(env->movcal_backup_tail) = r; *(env->movcal_backup_tail) = r;
env->movcal_backup_tail = &(r->next); env->movcal_backup_tail = &(r->next);
} }
} }
@ -129,12 +129,12 @@ void helper_discard_movcal_backup(CPUSH4State *env)
while(current) while(current)
{ {
memory_content *next = current->next; memory_content *next = current->next;
g_free(current); g_free(current);
env->movcal_backup = current = next; env->movcal_backup = current = next;
if (current == NULL) if (current == NULL)
env->movcal_backup_tail = &(env->movcal_backup); env->movcal_backup_tail = &(env->movcal_backup);
} }
} }
void helper_ocbi(CPUSH4State *env, uint32_t address) void helper_ocbi(CPUSH4State *env, uint32_t address)
@ -142,21 +142,21 @@ void helper_ocbi(CPUSH4State *env, uint32_t address)
memory_content **current = &(env->movcal_backup); memory_content **current = &(env->movcal_backup);
while (*current) while (*current)
{ {
uint32_t a = (*current)->address; uint32_t a = (*current)->address;
if ((a & ~0x1F) == (address & ~0x1F)) if ((a & ~0x1F) == (address & ~0x1F))
{ {
memory_content *next = (*current)->next; memory_content *next = (*current)->next;
cpu_stl_data(env, a, (*current)->value); cpu_stl_data(env, a, (*current)->value);
if (next == NULL) if (next == NULL)
{ {
env->movcal_backup_tail = current; env->movcal_backup_tail = current;
} }
g_free(*current); g_free(*current);
*current = next; *current = next;
break; break;
} }
} }
} }
@ -169,10 +169,10 @@ void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
env->mach = (res >> 32) & 0xffffffff; env->mach = (res >> 32) & 0xffffffff;
env->macl = res & 0xffffffff; env->macl = res & 0xffffffff;
if (env->sr & (1u << SR_S)) { if (env->sr & (1u << SR_S)) {
if (res < 0) if (res < 0)
env->mach |= 0xffff0000; env->mach |= 0xffff0000;
else else
env->mach &= 0x00007fff; env->mach &= 0x00007fff;
} }
} }
@ -185,13 +185,13 @@ void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
env->mach = (res >> 32) & 0xffffffff; env->mach = (res >> 32) & 0xffffffff;
env->macl = res & 0xffffffff; env->macl = res & 0xffffffff;
if (env->sr & (1u << SR_S)) { if (env->sr & (1u << SR_S)) {
if (res < -0x80000000) { if (res < -0x80000000) {
env->mach = 1; env->mach = 1;
env->macl = 0x80000000; env->macl = 0x80000000;
} else if (res > 0x000000007fffffff) { } else if (res > 0x000000007fffffff) {
env->mach = 1; env->mach = 1;
env->macl = 0x7fffffff; env->macl = 0x7fffffff;
} }
} }
} }
@ -199,9 +199,9 @@ void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
{ {
env->fpscr = val & FPSCR_MASK; env->fpscr = val & FPSCR_MASK;
if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) { if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
set_float_rounding_mode(float_round_to_zero, &env->fp_status); set_float_rounding_mode(float_round_to_zero, &env->fp_status);
} else { } else {
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
} }
set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status); set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
} }

1466
target/sh4/translate.c
View File

File diff suppressed because it is too large Load Diff