target-xtensa: implement windowed registers
See ISA, 4.7.1 for details. Physical registers and currently visible window are separate fields in CPUEnv. Only current window is accessible to TCG. On operations that change window base helpers copy current window to and from physical registers. Window overflow check described in 4.7.1.3 is in separate patch. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Max Filippov
Blue Swirl
parent
f76ebf55cd
commit
553e44f906
@ -108,6 +108,8 @@ enum {
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enum {
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SAR = 3,
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SCOMPARE1 = 12,
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WINDOW_BASE = 72,
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WINDOW_START = 73,
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EPC1 = 177,
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DEPC = 192,
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EXCSAVE1 = 209,
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@ -134,6 +136,8 @@ enum {
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#define PS_WOE 0x40000
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#define MAX_NAREG 64
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enum {
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/* Static vectors */
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EXC_RESET,
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@ -185,6 +189,7 @@ enum {
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typedef struct XtensaConfig {
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const char *name;
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uint64_t options;
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unsigned nareg;
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int excm_level;
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int ndepc;
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uint32_t exception_vector[EXC_MAX];
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@ -196,6 +201,7 @@ typedef struct CPUXtensaState {
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uint32_t pc;
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uint32_t sregs[256];
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uint32_t uregs[256];
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uint32_t phys_regs[MAX_NAREG];
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int exception_taken;
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@ -214,6 +220,8 @@ int cpu_xtensa_exec(CPUXtensaState *s);
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void do_interrupt(CPUXtensaState *s);
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int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
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void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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void xtensa_sync_window_from_phys(CPUState *env);
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void xtensa_sync_phys_from_window(CPUState *env);
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#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
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@ -45,6 +45,7 @@ static const XtensaConfig core_config[] = {
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{
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.name = "sample-xtensa-core",
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.options = -1,
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.nareg = 64,
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.ndepc = 1,
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.excm_level = 16,
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.exception_vector = {
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@ -5,5 +5,13 @@ DEF_HELPER_2(exception_cause, void, i32, i32)
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DEF_HELPER_3(exception_cause_vaddr, void, i32, i32, i32)
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DEF_HELPER_1(nsa, i32, i32)
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DEF_HELPER_1(nsau, i32, i32)
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DEF_HELPER_1(wsr_windowbase, void, i32)
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DEF_HELPER_3(entry, void, i32, i32, i32)
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DEF_HELPER_1(retw, i32, i32)
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DEF_HELPER_1(rotw, void, i32)
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DEF_HELPER_2(window_check, void, i32, i32)
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DEF_HELPER_0(restore_owb, void)
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DEF_HELPER_1(movsp, void, i32)
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DEF_HELPER_0(dump_state, void)
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#include "def-helper.h"
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@ -100,3 +100,195 @@ uint32_t HELPER(nsau)(uint32_t v)
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{
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return v ? clz32(v) : 32;
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}
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static void copy_window_from_phys(CPUState *env,
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uint32_t window, uint32_t phys, uint32_t n)
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{
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assert(phys < env->config->nareg);
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if (phys + n <= env->config->nareg) {
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memcpy(env->regs + window, env->phys_regs + phys,
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n * sizeof(uint32_t));
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} else {
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uint32_t n1 = env->config->nareg - phys;
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memcpy(env->regs + window, env->phys_regs + phys,
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n1 * sizeof(uint32_t));
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memcpy(env->regs + window + n1, env->phys_regs,
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(n - n1) * sizeof(uint32_t));
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}
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}
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static void copy_phys_from_window(CPUState *env,
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uint32_t phys, uint32_t window, uint32_t n)
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{
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assert(phys < env->config->nareg);
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if (phys + n <= env->config->nareg) {
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memcpy(env->phys_regs + phys, env->regs + window,
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n * sizeof(uint32_t));
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} else {
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uint32_t n1 = env->config->nareg - phys;
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memcpy(env->phys_regs + phys, env->regs + window,
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n1 * sizeof(uint32_t));
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memcpy(env->phys_regs, env->regs + window + n1,
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(n - n1) * sizeof(uint32_t));
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}
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}
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static inline unsigned windowbase_bound(unsigned a, const CPUState *env)
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{
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return a & (env->config->nareg / 4 - 1);
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}
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static inline unsigned windowstart_bit(unsigned a, const CPUState *env)
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{
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return 1 << windowbase_bound(a, env);
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}
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void xtensa_sync_window_from_phys(CPUState *env)
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{
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copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
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}
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void xtensa_sync_phys_from_window(CPUState *env)
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{
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copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
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}
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static void rotate_window_abs(uint32_t position)
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{
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xtensa_sync_phys_from_window(env);
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env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
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xtensa_sync_window_from_phys(env);
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}
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static void rotate_window(uint32_t delta)
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{
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rotate_window_abs(env->sregs[WINDOW_BASE] + delta);
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}
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void HELPER(wsr_windowbase)(uint32_t v)
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{
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rotate_window_abs(v);
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}
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void HELPER(entry)(uint32_t pc, uint32_t s, uint32_t imm)
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{
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int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
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if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
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qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
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pc, env->sregs[PS]);
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HELPER(exception_cause)(pc, ILLEGAL_INSTRUCTION_CAUSE);
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} else {
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env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
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rotate_window(callinc);
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env->sregs[WINDOW_START] |=
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windowstart_bit(env->sregs[WINDOW_BASE], env);
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}
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}
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void HELPER(window_check)(uint32_t pc, uint32_t w)
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{
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uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
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uint32_t windowstart = env->sregs[WINDOW_START];
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uint32_t m, n;
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if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) {
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return;
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}
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for (n = 1; ; ++n) {
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if (n > w) {
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return;
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}
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if (windowstart & windowstart_bit(windowbase + n, env)) {
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break;
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}
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}
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m = windowbase_bound(windowbase + n, env);
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rotate_window(n);
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env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
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(windowbase << PS_OWB_SHIFT) | PS_EXCM;
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env->sregs[EPC1] = env->pc = pc;
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if (windowstart & windowstart_bit(m + 1, env)) {
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HELPER(exception)(EXC_WINDOW_OVERFLOW4);
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} else if (windowstart & windowstart_bit(m + 2, env)) {
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HELPER(exception)(EXC_WINDOW_OVERFLOW8);
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} else {
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HELPER(exception)(EXC_WINDOW_OVERFLOW12);
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}
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}
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uint32_t HELPER(retw)(uint32_t pc)
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{
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int n = (env->regs[0] >> 30) & 0x3;
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int m = 0;
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uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
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uint32_t windowstart = env->sregs[WINDOW_START];
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uint32_t ret_pc = 0;
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if (windowstart & windowstart_bit(windowbase - 1, env)) {
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m = 1;
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} else if (windowstart & windowstart_bit(windowbase - 2, env)) {
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m = 2;
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} else if (windowstart & windowstart_bit(windowbase - 3, env)) {
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m = 3;
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}
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if (n == 0 || (m != 0 && m != n) ||
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((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
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qemu_log("Illegal retw instruction(pc = %08x), "
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"PS = %08x, m = %d, n = %d\n",
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pc, env->sregs[PS], m, n);
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HELPER(exception_cause)(pc, ILLEGAL_INSTRUCTION_CAUSE);
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} else {
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int owb = windowbase;
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ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
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rotate_window(-n);
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if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
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env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
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} else {
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/* window underflow */
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env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
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(windowbase << PS_OWB_SHIFT) | PS_EXCM;
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env->sregs[EPC1] = env->pc = pc;
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if (n == 1) {
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HELPER(exception)(EXC_WINDOW_UNDERFLOW4);
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} else if (n == 2) {
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HELPER(exception)(EXC_WINDOW_UNDERFLOW8);
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} else if (n == 3) {
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HELPER(exception)(EXC_WINDOW_UNDERFLOW12);
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}
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}
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}
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return ret_pc;
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}
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void HELPER(rotw)(uint32_t imm4)
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{
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rotate_window(imm4);
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}
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void HELPER(restore_owb)(void)
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{
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rotate_window_abs((env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
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}
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void HELPER(movsp)(uint32_t pc)
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{
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if ((env->sregs[WINDOW_START] &
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(windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
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windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
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windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
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HELPER(exception_cause)(pc, ALLOCA_CAUSE);
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}
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}
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void HELPER(dump_state)(void)
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{
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cpu_dump_state(env, stderr, fprintf, 0);
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}
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@ -67,6 +67,8 @@ static TCGv_i32 cpu_UR[256];
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static const char * const sregnames[256] = {
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[SAR] = "SAR",
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[SCOMPARE1] = "SCOMPARE1",
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[WINDOW_BASE] = "WINDOW_BASE",
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[WINDOW_START] = "WINDOW_START",
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[EPC1] = "EPC1",
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[DEPC] = "DEPC",
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[EXCSAVE1] = "EXCSAVE1",
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@ -217,6 +219,34 @@ static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
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tcg_temp_free(tmp);
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}
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static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
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int slot)
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{
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TCGv_i32 tcallinc = tcg_const_i32(callinc);
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tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
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tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
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tcg_temp_free(tcallinc);
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tcg_gen_movi_i32(cpu_R[callinc << 2],
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(callinc << 30) | (dc->next_pc & 0x3fffffff));
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gen_jump_slot(dc, dest, slot);
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}
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static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
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{
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gen_callw_slot(dc, callinc, dest, -1);
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}
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static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
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{
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TCGv_i32 tmp = tcg_const_i32(dest);
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if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
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slot = -1;
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}
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gen_callw_slot(dc, callinc, tmp, slot);
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tcg_temp_free(tmp);
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}
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static void gen_brcond(DisasContext *dc, TCGCond cond,
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TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
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{
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@ -263,6 +293,11 @@ static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
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dc->sar_m32_5bit = false;
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}
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static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
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{
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gen_helper_wsr_windowbase(v);
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}
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static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
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{
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uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
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@ -281,6 +316,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
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static void (* const wsr_handler[256])(DisasContext *dc,
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uint32_t sr, TCGv_i32 v) = {
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[SAR] = gen_wsr_sar,
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[WINDOW_BASE] = gen_wsr_windowbase,
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[PS] = gen_wsr_ps,
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};
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@ -429,7 +465,12 @@ static void disas_xtensa_insn(DisasContext *dc)
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case 1: /*RETWw*/
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HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
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TBD();
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{
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TCGv_i32 tmp = tcg_const_i32(dc->pc);
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gen_helper_retw(tmp, tmp);
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gen_jump(dc, tmp);
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tcg_temp_free(tmp);
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}
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break;
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case 3: /*reserved*/
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@ -454,7 +495,13 @@ static void disas_xtensa_insn(DisasContext *dc)
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case 2: /*CALLX8w*/
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case 3: /*CALLX12w*/
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HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
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TBD();
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
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gen_callw(dc, CALLX_N, tmp);
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tcg_temp_free(tmp);
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}
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break;
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}
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break;
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@ -463,7 +510,12 @@ static void disas_xtensa_insn(DisasContext *dc)
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case 1: /*MOVSPw*/
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HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
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TBD();
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{
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TCGv_i32 pc = tcg_const_i32(dc->pc);
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gen_helper_movsp(pc);
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tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
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tcg_temp_free(pc);
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}
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break;
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case 2: /*SYNC*/
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@ -523,7 +575,27 @@ static void disas_xtensa_insn(DisasContext *dc)
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case 4: /*RFWOw*/
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case 5: /*RFWUw*/
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HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
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TBD();
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gen_check_privilege(dc);
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{
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TCGv_i32 tmp = tcg_const_i32(1);
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tcg_gen_andi_i32(
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cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
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tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
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if (RRR_S == 4) {
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tcg_gen_andc_i32(cpu_SR[WINDOW_START],
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cpu_SR[WINDOW_START], tmp);
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} else {
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tcg_gen_or_i32(cpu_SR[WINDOW_START],
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cpu_SR[WINDOW_START], tmp);
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}
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gen_helper_restore_owb();
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gen_jump(dc, cpu_SR[EPC1]);
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tcg_temp_free(tmp);
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}
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break;
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default: /*reserved*/
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@ -670,7 +742,13 @@ static void disas_xtensa_insn(DisasContext *dc)
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case 8: /*ROTWw*/
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HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
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TBD();
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gen_check_privilege(dc);
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{
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TCGv_i32 tmp = tcg_const_i32(
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RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
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gen_helper_rotw(tmp);
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tcg_temp_free(tmp);
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}
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break;
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case 14: /*NSAu*/
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@ -1129,7 +1207,35 @@ static void disas_xtensa_insn(DisasContext *dc)
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break;
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case 9: /*LSC4*/
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TBD();
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switch (OP2) {
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case 0: /*L32E*/
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HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
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gen_check_privilege(dc);
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{
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TCGv_i32 addr = tcg_temp_new_i32();
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tcg_gen_addi_i32(addr, cpu_R[RRR_S],
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(0xffffffc0 | (RRR_R << 2)));
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tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
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tcg_temp_free(addr);
|
||||
}
|
||||
break;
|
||||
|
||||
case 4: /*S32E*/
|
||||
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
|
||||
gen_check_privilege(dc);
|
||||
{
|
||||
TCGv_i32 addr = tcg_temp_new_i32();
|
||||
tcg_gen_addi_i32(addr, cpu_R[RRR_S],
|
||||
(0xffffffc0 | (RRR_R << 2)));
|
||||
tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
|
||||
tcg_temp_free(addr);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
RESERVED();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 10: /*FP0*/
|
||||
@ -1368,7 +1474,8 @@ static void disas_xtensa_insn(DisasContext *dc)
|
||||
case 2: /*CALL8w*/
|
||||
case 3: /*CALL12w*/
|
||||
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
|
||||
TBD();
|
||||
gen_callwi(dc, CALL_N,
|
||||
(dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@ -1411,7 +1518,15 @@ static void disas_xtensa_insn(DisasContext *dc)
|
||||
switch (BRI8_M) {
|
||||
case 0: /*ENTRYw*/
|
||||
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
|
||||
TBD();
|
||||
{
|
||||
TCGv_i32 pc = tcg_const_i32(dc->pc);
|
||||
TCGv_i32 s = tcg_const_i32(BRI12_S);
|
||||
TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
|
||||
gen_helper_entry(pc, s, imm);
|
||||
tcg_temp_free(imm);
|
||||
tcg_temp_free(s);
|
||||
tcg_temp_free(pc);
|
||||
}
|
||||
break;
|
||||
|
||||
case 1: /*B1*/
|
||||
@ -1576,7 +1691,12 @@ static void disas_xtensa_insn(DisasContext *dc)
|
||||
|
||||
case 1: /*RETW.Nn*/
|
||||
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
|
||||
TBD();
|
||||
{
|
||||
TCGv_i32 tmp = tcg_const_i32(dc->pc);
|
||||
gen_helper_retw(tmp, tmp);
|
||||
gen_jump(dc, tmp);
|
||||
tcg_temp_free(tmp);
|
||||
}
|
||||
break;
|
||||
|
||||
case 2: /*BREAK.Nn*/
|
||||
@ -1750,6 +1870,13 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
|
||||
cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
|
||||
(i % 4) == 3 ? '\n' : ' ');
|
||||
}
|
||||
|
||||
cpu_fprintf(f, "\n");
|
||||
|
||||
for (i = 0; i < env->config->nareg; ++i) {
|
||||
cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
|
||||
(i % 4) == 3 ? '\n' : ' ');
|
||||
}
|
||||
}
|
||||
|
||||
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user