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target-openrisc: Use clz and ctz opcodes 

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2016-11-16 11:17:45 +01:00
parent 1a0196c5c7
commit 555baef8d0
3 changed files with 4 additions and 23 deletions
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2
target/openrisc/helper.h
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@ -54,8 +54,6 @@ FOP_CMP(ge)
#undef FOP_CMP
/* int */
DEF_HELPER_FLAGS_1(ff1, 0, tl, tl)
DEF_HELPER_FLAGS_1(fl1, 0, tl, tl)
DEF_HELPER_FLAGS_3(mul32, 0, i32, env, i32, i32)
/* interrupt */

19
target/openrisc/int_helper.c
View File

@ -24,25 +24,6 @@
#include "exception.h"
#include "qemu/host-utils.h"
target_ulong HELPER(ff1)(target_ulong x)
{
/*#ifdef TARGET_OPENRISC64
return x ? ctz64(x) + 1 : 0;
#else*/
return x ? ctz32(x) + 1 : 0;
/*#endif*/
}
target_ulong HELPER(fl1)(target_ulong x)
{
/* not used yet, open it when we need or64. */
/*#ifdef TARGET_OPENRISC64
return 64 - clz64(x);
#else*/
return 32 - clz32(x);
/*#endif*/
}
uint32_t HELPER(mul32)(CPUOpenRISCState *env,
uint32_t ra, uint32_t rb)
{

6
target/openrisc/translate.c
View File

@ -602,11 +602,13 @@ static void dec_calc(DisasContext *dc, uint32_t insn)
switch (op1) {
case 0x00: /* l.ff1 */
LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb);
gen_helper_ff1(cpu_R[rd], cpu_R[ra]);
tcg_gen_ctzi_tl(cpu_R[rd], cpu_R[ra], -1);
tcg_gen_addi_tl(cpu_R[rd], cpu_R[rd], 1);
break;
case 0x01: /* l.fl1 */
LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb);
gen_helper_fl1(cpu_R[rd], cpu_R[ra]);
tcg_gen_clzi_tl(cpu_R[rd], cpu_R[ra], TARGET_LONG_BITS);
tcg_gen_subfi_tl(cpu_R[rd], TARGET_LONG_BITS, cpu_R[rd]);
break;
default: