riscv: plic: Add a couple of mising sifive_plic_update calls
Claiming an interrupt and changing the source priority both potentially affect whether an interrupt is pending, thus we must re-compute xEIP. Note that we don't put the sifive_plic_update inside sifive_plic_claim so that the logging of a claim (and the resulting IRQ) happens before the state update, making the causal effect clear, and that we drop the explicit call to sifive_plic_print_state when claiming since sifive_plic_update already does that automatically at the end for us. This can result in both spurious interrupt storms if you fail to complete an IRQ before enabling interrupts (and no other actions occur that result in a call to sifive_plic_update), but also more importantly lost interrupts if a disabled interrupt is pending and then becomes enabled. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200618210649.22451-1-jrtc27@jrtc27.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -255,8 +255,8 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
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plic->addr_config[addrid].hartid,
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mode_to_char(plic->addr_config[addrid].mode),
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value);
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sifive_plic_print_state(plic);
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}
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sifive_plic_update(plic);
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return value;
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}
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}
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@ -287,6 +287,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
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qemu_log("plic: write priority: irq=%d priority=%d\n",
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irq, plic->source_priority[irq]);
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}
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sifive_plic_update(plic);
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return;
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} else if (addr >= plic->pending_base && /* 1 bit per source */
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addr < plic->pending_base + (plic->num_sources >> 3))
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