igb: packet-split descriptors support
Packet-split descriptors are used by Linux VF driver for MTU values from 2048 Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
Tomasz Dzieciol
Jason Wang
parent
1c4e67a5be
commit
560cf339b2
@ -267,6 +267,29 @@ igb_rx_use_legacy_descriptor(IGBCore *core)
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return false;
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}
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typedef struct E1000ERingInfo {
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int dbah;
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int dbal;
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int dlen;
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int dh;
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int dt;
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int idx;
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} E1000ERingInfo;
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static uint32_t
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igb_rx_queue_desctyp_get(IGBCore *core, const E1000ERingInfo *r)
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{
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return core->mac[E1000_SRRCTL(r->idx) >> 2] & E1000_SRRCTL_DESCTYPE_MASK;
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}
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static bool
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igb_rx_use_ps_descriptor(IGBCore *core, const E1000ERingInfo *r)
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{
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uint32_t desctyp = igb_rx_queue_desctyp_get(core, r);
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return desctyp == E1000_SRRCTL_DESCTYPE_HDR_SPLIT ||
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desctyp == E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
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}
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static inline bool
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igb_rss_enabled(IGBCore *core)
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{
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@ -694,15 +717,6 @@ static uint32_t igb_rx_wb_eic(IGBCore *core, int queue_idx)
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return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0;
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}
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typedef struct E1000ERingInfo {
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int dbah;
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int dbal;
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int dlen;
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int dh;
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int dt;
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int idx;
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} E1000ERingInfo;
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static inline bool
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igb_ring_empty(IGBCore *core, const E1000ERingInfo *r)
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{
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@ -1233,12 +1247,31 @@ igb_read_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc,
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}
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static inline void
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igb_read_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
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igb_read_adv_rx_single_buf_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
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hwaddr *buff_addr)
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{
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*buff_addr = le64_to_cpu(desc->read.pkt_addr);
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}
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static inline void
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igb_read_adv_rx_split_buf_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
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hwaddr *buff_addr)
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{
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buff_addr[0] = le64_to_cpu(desc->read.hdr_addr);
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buff_addr[1] = le64_to_cpu(desc->read.pkt_addr);
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}
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typedef struct IGBBAState {
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uint16_t written[IGB_MAX_PS_BUFFERS];
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uint8_t cur_idx;
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} IGBBAState;
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typedef struct IGBSplitDescriptorData {
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bool sph;
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bool hbo;
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size_t hdr_len;
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} IGBSplitDescriptorData;
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typedef struct IGBPacketRxDMAState {
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size_t size;
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size_t total_size;
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@ -1249,20 +1282,42 @@ typedef struct IGBPacketRxDMAState {
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uint32_t rx_desc_header_buf_size;
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struct iovec *iov;
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size_t iov_ofs;
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bool do_ps;
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bool is_first;
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uint16_t written;
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hwaddr ba;
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IGBBAState bastate;
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hwaddr ba[IGB_MAX_PS_BUFFERS];
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IGBSplitDescriptorData ps_desc_data;
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} IGBPacketRxDMAState;
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static inline void
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igb_read_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
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hwaddr *buff_addr)
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igb_read_rx_descr(IGBCore *core,
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union e1000_rx_desc_union *desc,
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IGBPacketRxDMAState *pdma_st,
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const E1000ERingInfo *r)
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{
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uint32_t desc_type;
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if (igb_rx_use_legacy_descriptor(core)) {
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igb_read_lgcy_rx_descr(core, &desc->legacy, buff_addr);
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} else {
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igb_read_adv_rx_descr(core, &desc->adv, buff_addr);
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igb_read_lgcy_rx_descr(core, &desc->legacy, &pdma_st->ba[1]);
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pdma_st->ba[0] = 0;
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return;
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}
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/* advanced header split descriptor */
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if (igb_rx_use_ps_descriptor(core, r)) {
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igb_read_adv_rx_split_buf_descr(core, &desc->adv, &pdma_st->ba[0]);
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return;
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}
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/* descriptor replication modes not supported */
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desc_type = igb_rx_queue_desctyp_get(core, r);
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if (desc_type != E1000_SRRCTL_DESCTYPE_ADV_ONEBUF) {
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trace_igb_wrn_rx_desc_modes_not_supp(desc_type);
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}
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/* advanced single buffer descriptor */
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igb_read_adv_rx_single_buf_descr(core, &desc->adv, &pdma_st->ba[1]);
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pdma_st->ba[0] = 0;
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}
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static void
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@ -1405,6 +1460,13 @@ igb_write_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc,
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desc->status = (uint8_t) le32_to_cpu(status_flags);
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}
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static bool
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igb_rx_ps_descriptor_split_always(IGBCore *core, const E1000ERingInfo *r)
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{
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uint32_t desctyp = igb_rx_queue_desctyp_get(core, r);
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return desctyp == E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
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}
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static uint16_t
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igb_rx_desc_get_packet_type(IGBCore *core, struct NetRxPkt *pkt, uint16_t etqf)
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{
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@ -1495,15 +1557,54 @@ igb_write_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
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}
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static inline void
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igb_write_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
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struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info,
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uint16_t etqf, bool ts, uint16_t length)
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igb_write_adv_ps_rx_descr(IGBCore *core,
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union e1000_adv_rx_desc *desc,
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struct NetRxPkt *pkt,
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const E1000E_RSSInfo *rss_info,
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const E1000ERingInfo *r,
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uint16_t etqf,
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bool ts,
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IGBPacketRxDMAState *pdma_st)
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{
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size_t pkt_len;
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uint16_t hdr_info = 0;
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if (pdma_st->do_ps) {
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pkt_len = pdma_st->bastate.written[1];
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} else {
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pkt_len = pdma_st->bastate.written[0] + pdma_st->bastate.written[1];
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}
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igb_write_adv_rx_descr(core, desc, pkt, rss_info, etqf, ts, pkt_len);
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hdr_info = (pdma_st->ps_desc_data.hdr_len << E1000_ADVRXD_HDR_LEN_OFFSET) &
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E1000_ADVRXD_ADV_HDR_LEN_MASK;
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hdr_info |= pdma_st->ps_desc_data.sph ? E1000_ADVRXD_HDR_SPH : 0;
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desc->wb.lower.lo_dword.hdr_info = cpu_to_le16(hdr_info);
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desc->wb.upper.status_error |= cpu_to_le32(
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pdma_st->ps_desc_data.hbo ? E1000_ADVRXD_ST_ERR_HBO_OFFSET : 0);
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}
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static inline void
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igb_write_rx_descr(IGBCore *core,
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union e1000_rx_desc_union *desc,
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struct NetRxPkt *pkt,
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const E1000E_RSSInfo *rss_info,
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uint16_t etqf,
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bool ts,
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IGBPacketRxDMAState *pdma_st,
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const E1000ERingInfo *r)
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{
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if (igb_rx_use_legacy_descriptor(core)) {
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igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, length);
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igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info,
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pdma_st->bastate.written[1]);
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} else if (igb_rx_use_ps_descriptor(core, r)) {
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igb_write_adv_ps_rx_descr(core, &desc->adv, pkt, rss_info, r, etqf, ts,
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pdma_st);
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} else {
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igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info,
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etqf, ts, length);
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etqf, ts, pdma_st->bastate.written[1]);
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}
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}
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@ -1564,26 +1665,179 @@ igb_rx_descr_threshold_hit(IGBCore *core, const E1000ERingInfo *rxi)
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((core->mac[E1000_SRRCTL(rxi->idx) >> 2] >> 20) & 31) * 16;
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}
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static bool
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igb_do_ps(IGBCore *core,
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const E1000ERingInfo *r,
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struct NetRxPkt *pkt,
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IGBPacketRxDMAState *pdma_st)
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{
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bool hasip4, hasip6;
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EthL4HdrProto l4hdr_proto;
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bool fragment;
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bool split_always;
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size_t bheader_size;
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size_t total_pkt_len;
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if (!igb_rx_use_ps_descriptor(core, r)) {
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return false;
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}
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total_pkt_len = net_rx_pkt_get_total_len(pkt);
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bheader_size = igb_rxhdrbufsize(core, r);
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split_always = igb_rx_ps_descriptor_split_always(core, r);
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if (split_always && total_pkt_len <= bheader_size) {
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pdma_st->ps_hdr_len = total_pkt_len;
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pdma_st->ps_desc_data.hdr_len = total_pkt_len;
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return true;
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}
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net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
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if (hasip4) {
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fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
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} else if (hasip6) {
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fragment = net_rx_pkt_get_ip6_info(pkt)->fragment;
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} else {
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pdma_st->ps_desc_data.hdr_len = bheader_size;
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goto header_not_handled;
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}
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if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) {
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pdma_st->ps_desc_data.hdr_len = bheader_size;
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goto header_not_handled;
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}
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/* no header splitting for SCTP */
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if (!fragment && (l4hdr_proto == ETH_L4_HDR_PROTO_UDP ||
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l4hdr_proto == ETH_L4_HDR_PROTO_TCP)) {
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pdma_st->ps_hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt);
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} else {
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pdma_st->ps_hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt);
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}
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pdma_st->ps_desc_data.sph = true;
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pdma_st->ps_desc_data.hdr_len = pdma_st->ps_hdr_len;
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if (pdma_st->ps_hdr_len > bheader_size) {
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pdma_st->ps_desc_data.hbo = true;
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goto header_not_handled;
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}
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return true;
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header_not_handled:
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if (split_always) {
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pdma_st->ps_hdr_len = bheader_size;
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return true;
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}
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return false;
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}
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static void
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igb_truncate_to_descriptor_size(IGBPacketRxDMAState *pdma_st, size_t *size)
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{
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if (pdma_st->do_ps && pdma_st->is_first) {
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if (*size > pdma_st->rx_desc_packet_buf_size + pdma_st->ps_hdr_len) {
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*size = pdma_st->rx_desc_packet_buf_size + pdma_st->ps_hdr_len;
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}
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} else {
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if (*size > pdma_st->rx_desc_packet_buf_size) {
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*size = pdma_st->rx_desc_packet_buf_size;
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}
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}
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}
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static inline void
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igb_write_hdr_frag_to_rx_buffers(IGBCore *core,
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PCIDevice *d,
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IGBPacketRxDMAState *pdma_st,
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const char *data,
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dma_addr_t data_len)
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{
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assert(data_len <= pdma_st->rx_desc_header_buf_size -
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pdma_st->bastate.written[0]);
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pci_dma_write(d,
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pdma_st->ba[0] + pdma_st->bastate.written[0],
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data, data_len);
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pdma_st->bastate.written[0] += data_len;
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pdma_st->bastate.cur_idx = 1;
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}
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static void
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igb_write_header_to_rx_buffers(IGBCore *core,
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struct NetRxPkt *pkt,
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PCIDevice *d,
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IGBPacketRxDMAState *pdma_st,
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size_t *copy_size)
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{
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size_t iov_copy;
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size_t ps_hdr_copied = 0;
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if (!pdma_st->is_first) {
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/* Leave buffer 0 of each descriptor except first */
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/* empty */
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pdma_st->bastate.cur_idx = 1;
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return;
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}
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do {
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iov_copy = MIN(pdma_st->ps_hdr_len - ps_hdr_copied,
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pdma_st->iov->iov_len - pdma_st->iov_ofs);
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igb_write_hdr_frag_to_rx_buffers(core, d, pdma_st,
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pdma_st->iov->iov_base,
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iov_copy);
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*copy_size -= iov_copy;
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ps_hdr_copied += iov_copy;
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pdma_st->iov_ofs += iov_copy;
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if (pdma_st->iov_ofs == pdma_st->iov->iov_len) {
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pdma_st->iov++;
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pdma_st->iov_ofs = 0;
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}
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} while (ps_hdr_copied < pdma_st->ps_hdr_len);
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pdma_st->is_first = false;
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}
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static void
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igb_write_payload_frag_to_rx_buffers(IGBCore *core,
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PCIDevice *d,
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hwaddr ba,
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uint16_t *written,
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uint32_t cur_buf_len,
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IGBPacketRxDMAState *pdma_st,
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const char *data,
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dma_addr_t data_len)
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{
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trace_igb_rx_desc_buff_write(ba, *written, data, data_len);
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pci_dma_write(d, ba + *written, data, data_len);
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*written += data_len;
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while (data_len > 0) {
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assert(pdma_st->bastate.cur_idx < IGB_MAX_PS_BUFFERS);
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uint32_t cur_buf_bytes_left =
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pdma_st->rx_desc_packet_buf_size -
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pdma_st->bastate.written[pdma_st->bastate.cur_idx];
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uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left);
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trace_igb_rx_desc_buff_write(
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pdma_st->bastate.cur_idx,
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pdma_st->ba[pdma_st->bastate.cur_idx],
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pdma_st->bastate.written[pdma_st->bastate.cur_idx],
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data,
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bytes_to_write);
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pci_dma_write(d,
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pdma_st->ba[pdma_st->bastate.cur_idx] +
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pdma_st->bastate.written[pdma_st->bastate.cur_idx],
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data, bytes_to_write);
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pdma_st->bastate.written[pdma_st->bastate.cur_idx] += bytes_to_write;
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data += bytes_to_write;
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data_len -= bytes_to_write;
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if (pdma_st->bastate.written[pdma_st->bastate.cur_idx] ==
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pdma_st->rx_desc_packet_buf_size) {
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pdma_st->bastate.cur_idx++;
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}
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}
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}
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static void
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@ -1600,9 +1854,7 @@ igb_write_payload_to_rx_buffers(IGBCore *core,
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while (*copy_size) {
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iov_copy = MIN(*copy_size, pdma_st->iov->iov_len - pdma_st->iov_ofs);
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igb_write_payload_frag_to_rx_buffers(core, d,
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pdma_st->ba,
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&pdma_st->written,
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pdma_st->rx_desc_packet_buf_size,
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pdma_st,
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pdma_st->iov->iov_base +
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pdma_st->iov_ofs,
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iov_copy);
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@ -1618,9 +1870,7 @@ igb_write_payload_to_rx_buffers(IGBCore *core,
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if (pdma_st->desc_offset + pdma_st->desc_size >= pdma_st->total_size) {
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/* Simulate FCS checksum presence in the last descriptor */
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igb_write_payload_frag_to_rx_buffers(core, d,
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pdma_st->ba,
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&pdma_st->written,
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pdma_st->rx_desc_packet_buf_size,
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pdma_st,
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(const char *) &fcs_pad,
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e1000x_fcs_len(core->mac));
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}
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@ -1634,7 +1884,7 @@ igb_write_to_rx_buffers(IGBCore *core,
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{
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size_t copy_size;
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if (!pdma_st->ba) {
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if (!(pdma_st->ba)[1] || (pdma_st->do_ps && !(pdma_st->ba[0]))) {
|
||||
/* as per intel docs; skip descriptors with null buf addr */
|
||||
trace_e1000e_rx_null_descriptor();
|
||||
return;
|
||||
@ -1648,6 +1898,14 @@ igb_write_to_rx_buffers(IGBCore *core,
|
||||
igb_truncate_to_descriptor_size(pdma_st, &pdma_st->desc_size);
|
||||
copy_size = pdma_st->size - pdma_st->desc_offset;
|
||||
igb_truncate_to_descriptor_size(pdma_st, ©_size);
|
||||
|
||||
/* For PS mode copy the packet header first */
|
||||
if (pdma_st->do_ps) {
|
||||
igb_write_header_to_rx_buffers(core, pkt, d, pdma_st, ©_size);
|
||||
} else {
|
||||
pdma_st->bastate.cur_idx = 1;
|
||||
}
|
||||
|
||||
igb_write_payload_to_rx_buffers(core, pkt, d, pdma_st, ©_size);
|
||||
}
|
||||
|
||||
@ -1678,8 +1936,10 @@ igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt,
|
||||
d = core->owner;
|
||||
}
|
||||
|
||||
pdma_st.do_ps = igb_do_ps(core, rxi, pkt, &pdma_st);
|
||||
|
||||
do {
|
||||
pdma_st.written = 0;
|
||||
memset(&pdma_st.bastate, 0, sizeof(IGBBAState));
|
||||
bool is_last = false;
|
||||
|
||||
if (igb_ring_empty(core, rxi)) {
|
||||
@ -1690,7 +1950,7 @@ igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt,
|
||||
pci_dma_read(d, base, &desc, rx_desc_len);
|
||||
trace_e1000e_rx_descr(rxi->idx, base, rx_desc_len);
|
||||
|
||||
igb_read_rx_descr(core, &desc, &pdma_st.ba);
|
||||
igb_read_rx_descr(core, &desc, &pdma_st, rxi);
|
||||
|
||||
igb_write_to_rx_buffers(core, pkt, d, &pdma_st);
|
||||
pdma_st.desc_offset += pdma_st.desc_size;
|
||||
@ -1698,8 +1958,12 @@ igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt,
|
||||
is_last = true;
|
||||
}
|
||||
|
||||
igb_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL,
|
||||
rss_info, etqf, ts, pdma_st.written);
|
||||
igb_write_rx_descr(core, &desc,
|
||||
is_last ? pkt : NULL,
|
||||
rss_info,
|
||||
etqf, ts,
|
||||
&pdma_st,
|
||||
rxi);
|
||||
igb_pci_dma_write_rx_desc(core, d, base, &desc, rx_desc_len);
|
||||
igb_ring_advance(core, rxi, rx_desc_len / E1000_MIN_RX_DESC_LEN);
|
||||
} while (pdma_st.desc_offset < pdma_st.total_size);
|
||||
|
||||
@ -452,6 +452,7 @@ union e1000_adv_rx_desc {
|
||||
#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
|
||||
#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
|
||||
#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
|
||||
#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
|
||||
#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
|
||||
#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
|
||||
#define E1000_SRRCTL_DROP_EN 0x80000000
|
||||
@ -699,6 +700,14 @@ union e1000_adv_rx_desc {
|
||||
#define E1000_ADVRXD_PKT_UDP BIT(5)
|
||||
#define E1000_ADVRXD_PKT_SCTP BIT(6)
|
||||
|
||||
#define IGB_MAX_PS_BUFFERS 2
|
||||
|
||||
#define E1000_ADVRXD_HDR_LEN_OFFSET (21 - 16)
|
||||
#define E1000_ADVRXD_ADV_HDR_LEN_MASK ((BIT(10) - 1) << \
|
||||
E1000_ADVRXD_HDR_LEN_OFFSET)
|
||||
#define E1000_ADVRXD_HDR_SPH BIT(15)
|
||||
#define E1000_ADVRXD_ST_ERR_HBO_OFFSET BIT(3 + 20)
|
||||
|
||||
static inline uint8_t igb_ivar_entry_rx(uint8_t i)
|
||||
{
|
||||
return i < 8 ? i * 4 : (i - 8) * 4 + 2;
|
||||
|
||||
@ -278,7 +278,7 @@ igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRITE: PHY[%u] UNHANDLED"
|
||||
igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, bool pfrstd) "Set extended link params: ASD check: %d, Speed select bypass: %d, PF reset done: %d"
|
||||
|
||||
igb_rx_desc_buff_size(uint32_t b) "buffer size: %u"
|
||||
igb_rx_desc_buff_write(uint64_t addr, uint16_t offset, const void* source, uint32_t len) "addr: 0x%"PRIx64", offset: %u, from: %p, length: %u"
|
||||
igb_rx_desc_buff_write(uint8_t idx, uint64_t addr, uint16_t offset, const void* source, uint32_t len) "buffer %u, addr: 0x%"PRIx64", offset: %u, from: %p, length: %u"
|
||||
|
||||
igb_rx_metadata_rss(uint32_t rss, uint16_t rss_pkt_type) "RSS data: rss: 0x%X, rss_pkt_type: 0x%X"
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user