hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng
Alistair Francis
parent
73f6ed97ac
commit
56f6e31e7b
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@ -1316,6 +1316,13 @@ F: include/hw/riscv/opentitan.h
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F: include/hw/char/ibex_uart.h
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F: include/hw/intc/ibex_plic.h
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Microchip PolarFire SoC Icicle Kit
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M: Bin Meng <bin.meng@windriver.com>
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L: qemu-riscv@nongnu.org
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S: Supported
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F: hw/riscv/microchip_pfsoc.c
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F: include/hw/riscv/microchip_pfsoc.h
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RX Machines
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-----------
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rx-gdbsim
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@ -10,3 +10,4 @@ CONFIG_SPIKE=y
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CONFIG_SIFIVE_E=y
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CONFIG_SIFIVE_U=y
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CONFIG_RISCV_VIRT=y
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CONFIG_MICROCHIP_PFSOC=y
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@ -48,3 +48,9 @@ config RISCV_VIRT
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select PCI_EXPRESS_GENERIC_BRIDGE
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select PFLASH_CFI01
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select SIFIVE
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config MICROCHIP_PFSOC
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bool
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select HART
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select SIFIVE
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select UNIMP
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@ -16,5 +16,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
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riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
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hw_arch += {'riscv': riscv_ss}
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@ -0,0 +1,312 @@
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/*
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* QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
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*
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* 0) CLINT (Core Level Interruptor)
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* 1) PLIC (Platform Level Interrupt Controller)
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* 2) eNVM (Embedded Non-Volatile Memory)
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*
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* This board currently generates devicetree dynamically that indicates at least
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* two harts and up to five harts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qemu/units.h"
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#include "qemu/cutils.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/irq.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/cpu/cluster.h"
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#include "target/riscv/cpu.h"
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#include "hw/misc/unimp.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/microchip_pfsoc.h"
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/*
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* The BIOS image used by this machine is called Hart Software Services (HSS).
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* See https://github.com/polarfire-soc/hart-software-services
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*/
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#define BIOS_FILENAME "hss.bin"
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#define RESET_VECTOR 0x20220000
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} microchip_pfsoc_memmap[] = {
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[MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 },
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[MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
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[MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
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[MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
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[MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
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[MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
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[MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
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[MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
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[MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
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[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
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[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
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[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
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[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
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[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
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[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
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[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
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[MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
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};
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static void microchip_pfsoc_soc_instance_init(Object *obj)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
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object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
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qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
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object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
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TYPE_RISCV_HART_ARRAY);
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qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
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qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
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qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
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TYPE_RISCV_CPU_SIFIVE_E51);
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qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
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object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
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qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
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object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
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TYPE_RISCV_HART_ARRAY);
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qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
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qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
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qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
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TYPE_RISCV_CPU_SIFIVE_U54);
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qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
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}
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static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
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const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
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MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
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MemoryRegion *envm_data = g_new(MemoryRegion, 1);
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char *plic_hart_config;
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size_t plic_hart_config_len;
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int i;
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sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
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/*
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* The cluster must be realized after the RISC-V hart array container,
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* as the container's CPU object is only created on realize, and the
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* CPU must exist and have been parented into the cluster before the
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* cluster is realized.
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*/
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qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
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qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
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/* E51 DTIM */
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memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
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memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
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memory_region_add_subregion(system_memory,
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memmap[MICROCHIP_PFSOC_E51_DTIM].base,
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e51_dtim_mem);
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/* Bus Error Units */
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create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
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create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
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create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
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create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
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create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
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/* CLINT */
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sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
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memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
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SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
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/* L2 cache controller */
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create_unimplemented_device("microchip.pfsoc.l2cc",
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memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
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/*
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* Add L2-LIM at reset size.
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* This should be reduced in size as the L2 Cache Controller WayEnable
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* register is incremented. Unfortunately I don't see a nice (or any) way
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* to handle reducing or blocking out the L2 LIM while still allowing it
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* be re returned to all enabled after a reset. For the time being, just
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* leave it enabled all the time. This won't break anything, but will be
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* too generous to misbehaving guests.
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*/
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memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
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memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
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memory_region_add_subregion(system_memory,
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memmap[MICROCHIP_PFSOC_L2LIM].base,
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l2lim_mem);
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/* create PLIC hart topology configuration string */
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plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
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ms->smp.cpus;
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plic_hart_config = g_malloc0(plic_hart_config_len);
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for (i = 0; i < ms->smp.cpus; i++) {
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if (i != 0) {
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strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
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plic_hart_config_len);
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} else {
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strncat(plic_hart_config, "M", plic_hart_config_len);
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}
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plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
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}
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/* PLIC */
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s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
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plic_hart_config, 0,
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MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
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MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
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MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
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MICROCHIP_PFSOC_PLIC_PENDING_BASE,
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MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
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MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
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MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
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MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
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memmap[MICROCHIP_PFSOC_PLIC].size);
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g_free(plic_hart_config);
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/* SYSREG */
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create_unimplemented_device("microchip.pfsoc.sysreg",
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memmap[MICROCHIP_PFSOC_SYSREG].base,
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memmap[MICROCHIP_PFSOC_SYSREG].size);
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/* MPUCFG */
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create_unimplemented_device("microchip.pfsoc.mpucfg",
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memmap[MICROCHIP_PFSOC_MPUCFG].base,
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memmap[MICROCHIP_PFSOC_MPUCFG].size);
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/* eNVM */
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memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
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memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
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&error_fatal);
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memory_region_add_subregion(system_memory,
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memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
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envm_data);
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/* IOSCBCFG */
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create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
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memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
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memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
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}
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static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = microchip_pfsoc_soc_realize;
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/* Reason: Uses serial_hds in realize function, thus can't be used twice */
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dc->user_creatable = false;
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}
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static const TypeInfo microchip_pfsoc_soc_type_info = {
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.name = TYPE_MICROCHIP_PFSOC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(MicrochipPFSoCState),
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.instance_init = microchip_pfsoc_soc_instance_init,
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.class_init = microchip_pfsoc_soc_class_init,
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};
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static void microchip_pfsoc_soc_register_types(void)
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{
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type_register_static(µchip_pfsoc_soc_type_info);
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}
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type_init(microchip_pfsoc_soc_register_types)
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static void microchip_icicle_kit_machine_init(MachineState *machine)
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{
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MachineClass *mc = MACHINE_GET_CLASS(machine);
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const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
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MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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/* Sanity check on RAM size */
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if (machine->ram_size < mc->default_ram_size) {
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char *sz = size_to_str(mc->default_ram_size);
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error_report("Invalid RAM size, should be bigger than %s", sz);
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g_free(sz);
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exit(EXIT_FAILURE);
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}
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/* Initialize SoC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc,
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TYPE_MICROCHIP_PFSOC);
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qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
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/* Register RAM */
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memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory,
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memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
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/* Load the firmware */
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riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
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}
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static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "Microchip PolarFire SoC Icicle Kit";
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mc->init = microchip_icicle_kit_machine_init;
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mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
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MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
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mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
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mc->default_cpus = mc->min_cpus;
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mc->default_ram_size = 1 * GiB;
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}
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static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
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.name = MACHINE_TYPE_NAME("microchip-icicle-kit"),
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.parent = TYPE_MACHINE,
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.class_init = microchip_icicle_kit_machine_class_init,
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.instance_size = sizeof(MicrochipIcicleKitState),
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};
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static void microchip_icicle_kit_machine_init_register_types(void)
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{
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type_register_static(µchip_icicle_kit_machine_typeinfo);
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||||
}
|
||||
|
||||
type_init(microchip_icicle_kit_machine_init_register_types)
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* Microchip PolarFire SoC machine interface
|
||||
*
|
||||
* Copyright (c) 2020 Wind River Systems, Inc.
|
||||
*
|
||||
* Author:
|
||||
* Bin Meng <bin.meng@windriver.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2 or later, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef HW_MICROCHIP_PFSOC_H
|
||||
#define HW_MICROCHIP_PFSOC_H
|
||||
|
||||
typedef struct MicrochipPFSoCState {
|
||||
/*< private >*/
|
||||
DeviceState parent_obj;
|
||||
|
||||
/*< public >*/
|
||||
CPUClusterState e_cluster;
|
||||
CPUClusterState u_cluster;
|
||||
RISCVHartArrayState e_cpus;
|
||||
RISCVHartArrayState u_cpus;
|
||||
DeviceState *plic;
|
||||
} MicrochipPFSoCState;
|
||||
|
||||
#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
|
||||
#define MICROCHIP_PFSOC(obj) \
|
||||
OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
|
||||
|
||||
typedef struct MicrochipIcicleKitState {
|
||||
/*< private >*/
|
||||
MachineState parent_obj;
|
||||
|
||||
/*< public >*/
|
||||
MicrochipPFSoCState soc;
|
||||
} MicrochipIcicleKitState;
|
||||
|
||||
#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
|
||||
MACHINE_TYPE_NAME("microchip-icicle-kit")
|
||||
#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
|
||||
OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
|
||||
TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
|
||||
|
||||
enum {
|
||||
MICROCHIP_PFSOC_DEBUG,
|
||||
MICROCHIP_PFSOC_E51_DTIM,
|
||||
MICROCHIP_PFSOC_BUSERR_UNIT0,
|
||||
MICROCHIP_PFSOC_BUSERR_UNIT1,
|
||||
MICROCHIP_PFSOC_BUSERR_UNIT2,
|
||||
MICROCHIP_PFSOC_BUSERR_UNIT3,
|
||||
MICROCHIP_PFSOC_BUSERR_UNIT4,
|
||||
MICROCHIP_PFSOC_CLINT,
|
||||
MICROCHIP_PFSOC_L2CC,
|
||||
MICROCHIP_PFSOC_L2LIM,
|
||||
MICROCHIP_PFSOC_PLIC,
|
||||
MICROCHIP_PFSOC_SYSREG,
|
||||
MICROCHIP_PFSOC_MPUCFG,
|
||||
MICROCHIP_PFSOC_ENVM_CFG,
|
||||
MICROCHIP_PFSOC_ENVM_DATA,
|
||||
MICROCHIP_PFSOC_IOSCB_CFG,
|
||||
MICROCHIP_PFSOC_DRAM,
|
||||
};
|
||||
|
||||
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
|
||||
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
|
||||
|
||||
#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS"
|
||||
#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
|
||||
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
|
||||
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
|
||||
#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
|
||||
#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
|
||||
#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
|
||||
#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000
|
||||
#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000
|
||||
|
||||
#endif /* HW_MICROCHIP_PFSOC_H */
|
||||
Loading…
Reference in New Issue