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target-ppc: Altivec 2.07: Vector SHA Sigma Instructions

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This patch adds the Vector SHA Sigma instructions introduced in Power
ISA Version 2.07:

  - Vector SHA-512 Sigma Doubleword (vshasigmad)
  - Vector SHA-256 Sigma Word (vshasigmaw)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Tom Musta 2014-02-12 15:23:18 -06:00 committed by Alexander Graf
parent 557d52fa69
commit 57354f8f12
3 changed files with 108 additions and 0 deletions
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2
target-ppc/helper.h
View File

@ -321,6 +321,8 @@ DEF_HELPER_3(vcipher, void, avr, avr, avr)
DEF_HELPER_3(vcipherlast, void, avr, avr, avr)
DEF_HELPER_3(vncipher, void, avr, avr, avr)
DEF_HELPER_3(vncipherlast, void, avr, avr, avr)
DEF_HELPER_3(vshasigmaw, void, avr, avr, i32)
DEF_HELPER_3(vshasigmad, void, avr, avr, i32)
DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)

82
target-ppc/int_helper.c
View File

@ -2618,6 +2618,88 @@ void helper_vncipherlast(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
r->u64[1] = vtemp2.u64[1] ^ b->u64[1];
}
#define ROTRu32(v, n) (((v) >> (n)) | ((v) << (32-n)))
#if defined(HOST_WORDS_BIGENDIAN)
#define EL_IDX(i) (i)
#else
#define EL_IDX(i) (3 - (i))
#endif
void helper_vshasigmaw(ppc_avr_t *r, ppc_avr_t *a, uint32_t st_six)
{
int st = (st_six & 0x10) != 0;
int six = st_six & 0xF;
int i;
VECTOR_FOR_INORDER_I(i, u32) {
if (st == 0) {
if ((six & (0x8 >> i)) == 0) {
r->u32[EL_IDX(i)] = ROTRu32(a->u32[EL_IDX(i)], 7) ^
ROTRu32(a->u32[EL_IDX(i)], 18) ^
(a->u32[EL_IDX(i)] >> 3);
} else { /* six.bit[i] == 1 */
r->u32[EL_IDX(i)] = ROTRu32(a->u32[EL_IDX(i)], 17) ^
ROTRu32(a->u32[EL_IDX(i)], 19) ^
(a->u32[EL_IDX(i)] >> 10);
}
} else { /* st == 1 */
if ((six & (0x8 >> i)) == 0) {
r->u32[EL_IDX(i)] = ROTRu32(a->u32[EL_IDX(i)], 2) ^
ROTRu32(a->u32[EL_IDX(i)], 13) ^
ROTRu32(a->u32[EL_IDX(i)], 22);
} else { /* six.bit[i] == 1 */
r->u32[EL_IDX(i)] = ROTRu32(a->u32[EL_IDX(i)], 6) ^
ROTRu32(a->u32[EL_IDX(i)], 11) ^
ROTRu32(a->u32[EL_IDX(i)], 25);
}
}
}
}
#undef ROTRu32
#undef EL_IDX
#define ROTRu64(v, n) (((v) >> (n)) | ((v) << (64-n)))
#if defined(HOST_WORDS_BIGENDIAN)
#define EL_IDX(i) (i)
#else
#define EL_IDX(i) (1 - (i))
#endif
void helper_vshasigmad(ppc_avr_t *r, ppc_avr_t *a, uint32_t st_six)
{
int st = (st_six & 0x10) != 0;
int six = st_six & 0xF;
int i;
VECTOR_FOR_INORDER_I(i, u64) {
if (st == 0) {
if ((six & (0x8 >> (2*i))) == 0) {
r->u64[EL_IDX(i)] = ROTRu64(a->u64[EL_IDX(i)], 1) ^
ROTRu64(a->u64[EL_IDX(i)], 8) ^
(a->u64[EL_IDX(i)] >> 7);
} else { /* six.bit[2*i] == 1 */
r->u64[EL_IDX(i)] = ROTRu64(a->u64[EL_IDX(i)], 19) ^
ROTRu64(a->u64[EL_IDX(i)], 61) ^
(a->u64[EL_IDX(i)] >> 6);
}
} else { /* st == 1 */
if ((six & (0x8 >> (2*i))) == 0) {
r->u64[EL_IDX(i)] = ROTRu64(a->u64[EL_IDX(i)], 28) ^
ROTRu64(a->u64[EL_IDX(i)], 34) ^
ROTRu64(a->u64[EL_IDX(i)], 39);
} else { /* six.bit[2*i] == 1 */
r->u64[EL_IDX(i)] = ROTRu64(a->u64[EL_IDX(i)], 14) ^
ROTRu64(a->u64[EL_IDX(i)], 18) ^
ROTRu64(a->u64[EL_IDX(i)], 41);
}
}
}
}
#undef ROTRu64
#undef EL_IDX
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX

24
target-ppc/translate.c
View File

@ -7438,6 +7438,27 @@ GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
#define VSHASIGMA(op) \
static void gen_##op(DisasContext *ctx) \
{ \
TCGv_ptr ra, rd; \
TCGv_i32 st_six; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
st_six = tcg_const_i32(rB(ctx->opcode)); \
gen_helper_##op(rd, ra, st_six); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rd); \
tcg_temp_free_i32(st_six); \
}
VSHASIGMA(vshasigmaw)
VSHASIGMA(vshasigmad)
/*** VSX extension ***/
static inline TCGv_i64 cpu_vsrh(int n)
@ -10698,6 +10719,9 @@ GEN_VXFORM_207(vsbox, 4, 23),
GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_207(vshasigmaw, 1, 26),
GEN_VXFORM_207(vshasigmad, 1, 27),
GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),