disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-14-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li
Alistair Francis
parent
77442380ec
commit
5748c886b1
173
disas/riscv.c
173
disas/riscv.c
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@ -156,6 +156,8 @@ typedef enum {
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rv_codec_css_swsp,
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rv_codec_css_sdsp,
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rv_codec_css_sqsp,
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rv_codec_k_bs,
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rv_codec_k_rnum,
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} rv_codec;
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typedef enum {
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@ -521,6 +523,43 @@ typedef enum {
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rv_op_bclr = 359,
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rv_op_binv = 360,
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rv_op_bext = 361,
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rv_op_aes32esmi = 362,
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rv_op_aes32esi = 363,
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rv_op_aes32dsmi = 364,
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rv_op_aes32dsi = 365,
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rv_op_aes64ks1i = 366,
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rv_op_aes64ks2 = 367,
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rv_op_aes64im = 368,
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rv_op_aes64esm = 369,
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rv_op_aes64es = 370,
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rv_op_aes64dsm = 371,
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rv_op_aes64ds = 372,
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rv_op_sha256sig0 = 373,
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rv_op_sha256sig1 = 374,
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rv_op_sha256sum0 = 375,
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rv_op_sha256sum1 = 376,
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rv_op_sha512sig0 = 377,
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rv_op_sha512sig1 = 378,
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rv_op_sha512sum0 = 379,
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rv_op_sha512sum1 = 380,
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rv_op_sha512sum0r = 381,
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rv_op_sha512sum1r = 382,
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rv_op_sha512sig0l = 383,
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rv_op_sha512sig0h = 384,
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rv_op_sha512sig1l = 385,
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rv_op_sha512sig1h = 386,
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rv_op_sm3p0 = 387,
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rv_op_sm3p1 = 388,
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rv_op_sm4ed = 389,
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rv_op_sm4ks = 390,
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rv_op_brev8 = 391,
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rv_op_pack = 392,
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rv_op_packh = 393,
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rv_op_packw = 394,
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rv_op_unzip = 395,
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rv_op_zip = 396,
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rv_op_xperm4 = 397,
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rv_op_xperm8 = 398,
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} rv_op;
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/* structures */
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@ -540,6 +579,8 @@ typedef struct {
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uint8_t succ;
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uint8_t aq;
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uint8_t rl;
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uint8_t bs;
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uint8_t rnum;
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} rv_decode;
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typedef struct {
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@ -615,6 +656,8 @@ static const char rv_freg_name_sym[32][5] = {
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#define rv_fmt_rd_rs2 "O\t0,2"
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#define rv_fmt_rs1_offset "O\t1,o"
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#define rv_fmt_rs2_offset "O\t2,o"
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#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
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#define rv_fmt_rd_rs1_rnum "O\t0,1,n"
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/* pseudo-instruction constraints */
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@ -766,6 +809,7 @@ static const rv_comp_data rvcp_csrrw[] = {
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{ rv_op_illegal, NULL }
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};
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static const rv_comp_data rvcp_csrrs[] = {
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{ rv_op_rdcycle, rvcc_rdcycle },
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{ rv_op_rdtime, rvcc_rdtime },
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@ -1203,6 +1247,43 @@ const rv_opcode_data opcode_data[] = {
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{ "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
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{ "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
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{ "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
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{ "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
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{ "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
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{ "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
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{ "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
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{ "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
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{ "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
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{ "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
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{ "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
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{ "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
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{ "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
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{ "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
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{ "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
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};
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/* CSR names */
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@ -1216,6 +1297,7 @@ static const char *csr_name(int csrno)
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case 0x0003: return "fcsr";
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case 0x0004: return "uie";
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case 0x0005: return "utvec";
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case 0x0015: return "seed";
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case 0x0040: return "uscratch";
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case 0x0041: return "uepc";
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case 0x0042: return "ucause";
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@ -1594,7 +1676,36 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 1:
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switch (((inst >> 27) & 0b11111)) {
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case 0b00000: op = rv_op_slli; break;
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case 0b00001:
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switch (((inst >> 20) & 0b1111111)) {
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case 0b0001111: op = rv_op_zip; break;
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}
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break;
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case 0b00010:
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switch (((inst >> 20) & 0b1111111)) {
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case 0b0000000: op = rv_op_sha256sum0; break;
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case 0b0000001: op = rv_op_sha256sum1; break;
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case 0b0000010: op = rv_op_sha256sig0; break;
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case 0b0000011: op = rv_op_sha256sig1; break;
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case 0b0000100: op = rv_op_sha512sum0; break;
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case 0b0000101: op = rv_op_sha512sum1; break;
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case 0b0000110: op = rv_op_sha512sig0; break;
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case 0b0000111: op = rv_op_sha512sig1; break;
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case 0b0001000: op = rv_op_sm3p0; break;
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case 0b0001001: op = rv_op_sm3p1; break;
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}
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break;
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case 0b00101: op = rv_op_bseti; break;
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case 0b00110:
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switch (((inst >> 20) & 0b1111111)) {
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case 0b0000000: op = rv_op_aes64im; break;
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default:
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if (((inst >> 24) & 0b0111) == 0b001) {
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op = rv_op_aes64ks1i;
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}
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break;
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}
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break;
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case 0b01001: op = rv_op_bclri; break;
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case 0b01101: op = rv_op_binvi; break;
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case 0b01100:
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@ -1615,13 +1726,20 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 5:
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switch (((inst >> 27) & 0b11111)) {
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case 0b00000: op = rv_op_srli; break;
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case 0b00001:
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switch (((inst >> 20) & 0b1111111)) {
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case 0b0001111: op = rv_op_unzip; break;
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}
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break;
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case 0b00101: op = rv_op_orc_b; break;
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case 0b01000: op = rv_op_srai; break;
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case 0b01001: op = rv_op_bexti; break;
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case 0b01100: op = rv_op_rori; break;
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case 0b01101:
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switch ((inst >> 20) & 0b1111111) {
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case 0b0011000: op = rv_op_rev8; break;
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case 0b0111000: op = rv_op_rev8; break;
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case 0b0000111: op = rv_op_brev8; break;
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}
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break;
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}
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@ -1742,8 +1860,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 36:
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switch ((inst >> 20) & 0b11111) {
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case 0: op = rv_op_zext_h; break;
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default: op = rv_op_pack; break;
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}
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break;
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case 39: op = rv_op_packh; break;
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case 41: op = rv_op_clmul; break;
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case 42: op = rv_op_clmulr; break;
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case 43: op = rv_op_clmulh; break;
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@ -1755,6 +1876,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 132: op = rv_op_sh2add; break;
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case 134: op = rv_op_sh3add; break;
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case 161: op = rv_op_bset; break;
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case 162: op = rv_op_xperm4; break;
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case 164: op = rv_op_xperm8; break;
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case 200: op = rv_op_aes64es; break;
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case 216: op = rv_op_aes64esm; break;
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case 232: op = rv_op_aes64ds; break;
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case 248: op = rv_op_aes64dsm; break;
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case 256: op = rv_op_sub; break;
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case 260: op = rv_op_xnor; break;
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case 261: op = rv_op_sra; break;
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@ -1762,9 +1889,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 263: op = rv_op_andn; break;
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case 289: op = rv_op_bclr; break;
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case 293: op = rv_op_bext; break;
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case 320: op = rv_op_sha512sum0r; break;
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case 328: op = rv_op_sha512sum1r; break;
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case 336: op = rv_op_sha512sig0l; break;
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case 344: op = rv_op_sha512sig1l; break;
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case 368: op = rv_op_sha512sig0h; break;
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case 376: op = rv_op_sha512sig1h; break;
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case 385: op = rv_op_rol; break;
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case 386: op = rv_op_ror; break;
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case 389: op = rv_op_ror; break;
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case 417: op = rv_op_binv; break;
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case 504: op = rv_op_aes64ks2; break;
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}
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switch ((inst >> 25) & 0b0011111) {
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case 17: op = rv_op_aes32esi; break;
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case 19: op = rv_op_aes32esmi; break;
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case 21: op = rv_op_aes32dsi; break;
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case 23: op = rv_op_aes32dsmi; break;
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case 24: op = rv_op_sm4ed; break;
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case 26: op = rv_op_sm4ks; break;
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}
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break;
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case 13: op = rv_op_lui; break;
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@ -1782,6 +1924,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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case 36:
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switch ((inst >> 20) & 0b11111) {
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case 0: op = rv_op_zext_h; break;
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default: op = rv_op_packw; break;
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}
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break;
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case 130: op = rv_op_sh1add_uw; break;
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@ -2374,6 +2517,16 @@ static uint32_t operand_cimmq(rv_inst inst)
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((inst << 57) >> 62) << 6;
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}
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static uint32_t operand_bs(rv_inst inst)
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{
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return (inst << 32) >> 62;
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}
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static uint32_t operand_rnum(rv_inst inst)
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{
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return (inst << 40) >> 60;
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}
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/* decode operands */
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static void decode_inst_operands(rv_decode *dec)
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@ -2653,6 +2806,16 @@ static void decode_inst_operands(rv_decode *dec)
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dec->rs2 = operand_crs2(inst);
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dec->imm = operand_cimmsqsp(inst);
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break;
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case rv_codec_k_bs:
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dec->rs1 = operand_rs1(inst);
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dec->rs2 = operand_rs2(inst);
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dec->bs = operand_bs(inst);
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break;
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case rv_codec_k_rnum:
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dec->rd = operand_rd(inst);
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dec->rs1 = operand_rs1(inst);
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dec->rnum = operand_rnum(inst);
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break;
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};
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}
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@ -2812,6 +2975,14 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
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case ')':
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append(buf, ")", buflen);
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break;
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case 'b':
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snprintf(tmp, sizeof(tmp), "%d", dec->bs);
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append(buf, tmp, buflen);
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break;
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case 'n':
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snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
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append(buf, tmp, buflen);
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break;
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case '0':
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append(buf, rv_ireg_name_sym[dec->rd], buflen);
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break;
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