initial APIC support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1183 c046a42c-6fe2-441c-8c8c-71466251a162
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bellard
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441
hw/apic.c
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441
hw/apic.c
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/*
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* APIC support
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "vl.h"
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//#define DEBUG_APIC
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/* APIC Local Vector Table */
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_THERMAL 1
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#define APIC_LVT_PERFORM 2
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#define APIC_LVT_LINT0 3
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#define APIC_LVT_LINT1 4
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#define APIC_LVT_ERROR 5
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#define APIC_LVT_NB 6
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/* APIC delivery modes */
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#define APIC_DM_FIXED 0
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#define APIC_DM_LOWPRI 1
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#define APIC_DM_SMI 2
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#define APIC_DM_NMI 4
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#define APIC_DM_INIT 5
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#define APIC_DM_SIPI 6
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#define APIC_DM_EXTINT 7
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#define APIC_TRIGGER_EDGE 0
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#define APIC_TRIGGER_LEVEL 1
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#define APIC_LVT_TIMER_PERIODIC (1<<17)
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#define APIC_LVT_MASKED (1<<16)
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#define APIC_LVT_LEVEL_TRIGGER (1<<15)
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#define APIC_LVT_REMOTE_IRR (1<<14)
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#define APIC_INPUT_POLARITY (1<<13)
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#define APIC_SEND_PENDING (1<<12)
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#define ESR_ILLEGAL_ADDRESS (1 << 7)
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#define APIC_SV_ENABLE (1 << 8)
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typedef struct APICState {
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CPUState *cpu_env;
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uint32_t apicbase;
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uint8_t id;
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uint8_t tpr;
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uint32_t spurious_vec;
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uint32_t isr[8]; /* in service register */
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uint32_t tmr[8]; /* trigger mode register */
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uint32_t irr[8]; /* interrupt request register */
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uint32_t lvt[APIC_LVT_NB];
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uint32_t esr; /* error register */
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uint32_t icr[2];
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uint32_t divide_conf;
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int count_shift;
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uint32_t initial_count;
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int64_t initial_count_load_time, next_time;
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QEMUTimer *timer;
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} APICState;
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static int apic_io_memory;
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void cpu_set_apic_base(CPUState *env, uint64_t val)
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{
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APICState *s = env->apic_state;
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#ifdef DEBUG_APIC
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printf("cpu_set_apic_base: %016llx\n", val);
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#endif
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s->apicbase = (val & 0xfffff000) |
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(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
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/* if disabled, cannot be enabled again */
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if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
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env->cpuid_features &= ~CPUID_APIC;
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s->spurious_vec &= ~APIC_SV_ENABLE;
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}
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}
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uint64_t cpu_get_apic_base(CPUState *env)
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{
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APICState *s = env->apic_state;
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#ifdef DEBUG_APIC
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printf("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase);
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#endif
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return s->apicbase;
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}
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/* return -1 if no bit is set */
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static int get_highest_priority_int(uint32_t *tab)
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{
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int i;
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for(i = 0;i < 8; i++) {
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if (tab[i] != 0) {
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return i * 32 + ffs(tab[i]) - 1;
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}
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}
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return -1;
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}
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static inline void set_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] |= mask;
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}
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static inline void reset_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] &= ~mask;
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}
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static int apic_get_ppr(APICState *s)
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{
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int tpr, isrv, ppr;
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tpr = (s->tpr >> 4);
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isrv = get_highest_priority_int(s->isr);
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if (isrv < 0)
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isrv = 0;
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isrv >>= 4;
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if (tpr >= isrv)
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ppr = s->tpr;
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else
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ppr = isrv << 4;
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return ppr;
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}
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/* signal the CPU if an irq is pending */
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static void apic_update_irq(APICState *s)
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{
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int irrv, isrv;
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irrv = get_highest_priority_int(s->irr);
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if (irrv < 0)
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return;
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isrv = get_highest_priority_int(s->isr);
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/* if the pending irq has less priority, we do not make a new request */
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if (isrv >= 0 && irrv >= isrv)
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return;
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
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}
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
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{
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set_bit(s->irr, vector_num);
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if (trigger_mode)
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set_bit(s->tmr, vector_num);
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else
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reset_bit(s->tmr, vector_num);
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apic_update_irq(s);
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}
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static void apic_eoi(APICState *s)
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{
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int isrv;
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isrv = get_highest_priority_int(s->isr);
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if (isrv < 0)
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return;
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reset_bit(s->isr, isrv);
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apic_update_irq(s);
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}
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int apic_get_interrupt(CPUState *env)
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{
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APICState *s = env->apic_state;
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int intno;
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/* if the APIC is installed or enabled, we let the 8259 handle the
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IRQs */
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if (!s)
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return -1;
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if (!(s->spurious_vec & APIC_SV_ENABLE))
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return -1;
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/* XXX: spurious IRQ handling */
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intno = get_highest_priority_int(s->irr);
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if (intno < 0)
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return -1;
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reset_bit(s->irr, intno);
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set_bit(s->isr, intno);
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apic_update_irq(s);
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return intno;
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}
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static uint32_t apic_get_current_count(APICState *s)
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{
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int64_t d;
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uint32_t val;
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d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
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s->count_shift;
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if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
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/* periodic */
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val = s->initial_count - (d % (s->initial_count + 1));
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} else {
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if (d >= s->initial_count)
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val = 0;
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else
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val = s->initial_count - d;
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}
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return val;
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}
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static void apic_timer_update(APICState *s, int64_t current_time)
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{
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int64_t next_time, d;
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if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
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d = (current_time - s->initial_count_load_time) >>
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s->count_shift;
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if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
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d = ((d / (s->initial_count + 1)) + 1) * (s->initial_count + 1);
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} else {
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if (d >= s->initial_count)
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goto no_timer;
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d = s->initial_count + 1;
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}
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next_time = s->initial_count_load_time + (d << s->count_shift);
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qemu_mod_timer(s->timer, next_time);
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s->next_time = next_time;
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} else {
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no_timer:
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qemu_del_timer(s->timer);
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}
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}
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static void apic_timer(void *opaque)
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{
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APICState *s = opaque;
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if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
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apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
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}
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apic_timer_update(s, s->next_time);
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}
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static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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return 0;
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}
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static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
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{
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return 0;
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}
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static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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}
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static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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}
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static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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CPUState *env;
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APICState *s;
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uint32_t val;
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int index;
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env = cpu_single_env;
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if (!env)
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return 0;
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s = env->apic_state;
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index = (addr >> 4) & 0xff;
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switch(index) {
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case 0x02: /* id */
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val = s->id << 24;
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break;
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case 0x03: /* version */
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val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
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break;
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case 0x08:
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val = s->tpr;
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break;
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case 0x0a:
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/* ppr */
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val = apic_get_ppr(s);
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break;
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case 0x0f:
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val = s->spurious_vec;
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break;
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case 0x10 ... 0x17:
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val = s->isr[index & 7];
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break;
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case 0x18 ... 0x1f:
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val = s->tmr[index & 7];
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break;
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case 0x20 ... 0x27:
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val = s->irr[index & 7];
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break;
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case 0x28:
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val = s->esr;
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break;
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case 0x32 ... 0x37:
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val = s->lvt[index - 0x32];
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break;
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case 0x30:
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case 0x31:
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val = s->icr[index & 1];
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break;
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case 0x38:
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val = s->initial_count;
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break;
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case 0x39:
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val = apic_get_current_count(s);
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break;
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case 0x3e:
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val = s->divide_conf;
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break;
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default:
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s->esr |= ESR_ILLEGAL_ADDRESS;
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val = 0;
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break;
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}
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#ifdef DEBUG_APIC
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printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
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#endif
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return val;
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}
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static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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CPUState *env;
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APICState *s;
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int index;
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env = cpu_single_env;
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if (!env)
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return;
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s = env->apic_state;
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#ifdef DEBUG_APIC
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printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
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#endif
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index = (addr >> 4) & 0xff;
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switch(index) {
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case 0x02:
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s->id = (val >> 24);
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break;
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case 0x08:
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s->tpr = val;
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break;
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case 0x0b: /* EOI */
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apic_eoi(s);
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break;
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case 0x0f:
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s->spurious_vec = val & 0x1ff;
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break;
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case 0x30:
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case 0x31:
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s->icr[index & 1] = val;
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break;
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case 0x32 ... 0x37:
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{
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int n = index - 0x32;
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s->lvt[n] = val;
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if (n == APIC_LVT_TIMER)
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apic_timer_update(s, qemu_get_clock(vm_clock));
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}
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break;
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case 0x38:
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s->initial_count = val;
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s->initial_count_load_time = qemu_get_clock(vm_clock);
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apic_timer_update(s, s->initial_count_load_time);
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break;
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case 0x3e:
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{
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int v;
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s->divide_conf = val & 0xb;
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v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
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s->count_shift = (v + 1) & 7;
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}
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break;
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default:
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s->esr |= ESR_ILLEGAL_ADDRESS;
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break;
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}
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}
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static CPUReadMemoryFunc *apic_mem_read[3] = {
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apic_mem_readb,
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apic_mem_readw,
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apic_mem_readl,
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};
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static CPUWriteMemoryFunc *apic_mem_write[3] = {
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apic_mem_writeb,
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apic_mem_writew,
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apic_mem_writel,
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};
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int apic_init(CPUState *env)
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{
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APICState *s;
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int i;
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s = malloc(sizeof(APICState));
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if (!s)
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return -1;
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memset(s, 0, sizeof(*s));
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env->apic_state = s;
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s->cpu_env = env;
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s->apicbase = 0xfee00000 |
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MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
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for(i = 0; i < APIC_LVT_NB; i++)
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s->lvt[i] = 1 << 16; /* mask LVT */
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s->spurious_vec = 0xff;
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if (apic_io_memory == 0) {
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/* NOTE: the APIC is directly connected to the CPU - it is not
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on the global memory bus. */
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apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
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apic_mem_write, NULL);
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cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, apic_io_memory);
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}
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s->timer = qemu_new_timer(vm_clock, apic_timer, s);
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return 0;
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}
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