x86_iommu/amd: Prepare for interrupt remap support
Register the interrupt remapping callback and read/write ops for the amd-iommu-ir memory region. amd-iommu-ir is set to higher priority to ensure that this region won't be masked out by other memory regions. Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Cc: Peter Xu <peterx@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Cc: Tom Lendacky <Thomas.Lendacky@amd.com> Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Singh, Brijesh
Michael S. Tsirkin
parent
53244386b0
commit
577c470f43
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@ -26,6 +26,7 @@
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#include "amd_iommu.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "hw/i386/apic_internal.h"
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#include "trace.h"
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/* used AMD-Vi MMIO registers */
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@ -1031,6 +1032,99 @@ static IOMMUTLBEntry amdvi_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
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return ret;
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}
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/* Interrupt remapping for MSI/MSI-X entry */
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static int amdvi_int_remap_msi(AMDVIState *iommu,
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MSIMessage *origin,
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MSIMessage *translated,
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uint16_t sid)
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{
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assert(origin && translated);
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trace_amdvi_ir_remap_msi_req(origin->address, origin->data, sid);
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if (!iommu || !X86_IOMMU_DEVICE(iommu)->intr_supported) {
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memcpy(translated, origin, sizeof(*origin));
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goto out;
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}
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if (origin->address & AMDVI_MSI_ADDR_HI_MASK) {
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trace_amdvi_err("MSI address high 32 bits non-zero when "
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"Interrupt Remapping enabled.");
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return -AMDVI_IR_ERR;
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}
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if ((origin->address & AMDVI_MSI_ADDR_LO_MASK) != APIC_DEFAULT_ADDRESS) {
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trace_amdvi_err("MSI is not from IOAPIC.");
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return -AMDVI_IR_ERR;
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}
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out:
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trace_amdvi_ir_remap_msi(origin->address, origin->data,
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translated->address, translated->data);
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return 0;
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}
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static int amdvi_int_remap(X86IOMMUState *iommu,
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MSIMessage *origin,
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MSIMessage *translated,
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uint16_t sid)
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{
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return amdvi_int_remap_msi(AMD_IOMMU_DEVICE(iommu), origin,
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translated, sid);
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}
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static MemTxResult amdvi_mem_ir_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size,
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MemTxAttrs attrs)
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{
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int ret;
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MSIMessage from = { 0, 0 }, to = { 0, 0 };
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uint16_t sid = AMDVI_IOAPIC_SB_DEVID;
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from.address = (uint64_t) addr + AMDVI_INT_ADDR_FIRST;
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from.data = (uint32_t) value;
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trace_amdvi_mem_ir_write_req(addr, value, size);
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if (!attrs.unspecified) {
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/* We have explicit Source ID */
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sid = attrs.requester_id;
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}
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ret = amdvi_int_remap_msi(opaque, &from, &to, sid);
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if (ret < 0) {
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/* TODO: log the event using IOMMU log event interface */
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error_report_once("failed to remap interrupt from devid 0x%x", sid);
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return MEMTX_ERROR;
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}
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apic_get_class()->send_msi(&to);
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trace_amdvi_mem_ir_write(to.address, to.data);
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return MEMTX_OK;
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}
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static MemTxResult amdvi_mem_ir_read(void *opaque, hwaddr addr,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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{
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return MEMTX_OK;
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}
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static const MemoryRegionOps amdvi_ir_ops = {
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.read_with_attrs = amdvi_mem_ir_read,
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.write_with_attrs = amdvi_mem_ir_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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}
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};
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static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
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{
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char name[128];
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@ -1066,6 +1160,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
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* |-----------------+-------------------+----------+
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* | amdvi_root | 00000000-ffffffff | 0 |
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* | amdvi_iommu | 00000000-ffffffff | 1 |
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* | amdvi_iommu_ir | fee00000-feefffff | 64 |
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* |-----------------+-------------------+----------|
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*/
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memory_region_init_iommu(&amdvi_dev_as->iommu,
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@ -1076,6 +1171,13 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
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memory_region_init(&amdvi_dev_as->root, OBJECT(s),
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"amdvi_root", UINT64_MAX);
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address_space_init(&amdvi_dev_as->as, &amdvi_dev_as->root, name);
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memory_region_init_io(&amdvi_dev_as->iommu_ir, OBJECT(s),
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&amdvi_ir_ops, s, "amd_iommu_ir",
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AMDVI_INT_ADDR_SIZE);
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memory_region_add_subregion_overlap(&amdvi_dev_as->root,
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AMDVI_INT_ADDR_FIRST,
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&amdvi_dev_as->iommu_ir,
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64);
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memory_region_add_subregion_overlap(&amdvi_dev_as->root, 0,
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MEMORY_REGION(&amdvi_dev_as->iommu),
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1);
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@ -1196,6 +1298,9 @@ static void amdvi_realize(DeviceState *dev, Error **err)
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return;
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}
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/* Pseudo address space under root PCI bus. */
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pcms->ioapic_as = amdvi_host_dma_iommu(bus, s, AMDVI_IOAPIC_SB_DEVID);
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/* set up MMIO */
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memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mmio",
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AMDVI_MMIO_SIZE);
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@ -1229,6 +1334,7 @@ static void amdvi_class_init(ObjectClass *klass, void* data)
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dc->vmsd = &vmstate_amdvi;
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dc->hotpluggable = false;
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dc_class->realize = amdvi_realize;
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dc_class->int_remap = amdvi_int_remap;
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/* Supported by the pc-q35-* machine types */
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dc->user_creatable = true;
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}
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@ -206,8 +206,18 @@
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#define AMDVI_COMMAND_SIZE 16
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#define AMDVI_INT_ADDR_FIRST 0xfee00000
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#define AMDVI_INT_ADDR_LAST 0xfeefffff
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#define AMDVI_INT_ADDR_FIRST 0xfee00000
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#define AMDVI_INT_ADDR_LAST 0xfeefffff
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#define AMDVI_INT_ADDR_SIZE (AMDVI_INT_ADDR_LAST - AMDVI_INT_ADDR_FIRST + 1)
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#define AMDVI_MSI_ADDR_HI_MASK (0xffffffff00000000ULL)
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#define AMDVI_MSI_ADDR_LO_MASK (0x00000000ffffffffULL)
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/* SB IOAPIC is always on this device in AMD systems */
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#define AMDVI_IOAPIC_SB_DEVID PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
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/* Interrupt remapping errors */
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#define AMDVI_IR_ERR 0x1
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#define TYPE_AMD_IOMMU_DEVICE "amd-iommu"
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#define AMD_IOMMU_DEVICE(obj)\
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@ -101,6 +101,11 @@ amdvi_mode_invalid(uint8_t level, uint64_t addr)"error: translation level 0x%"PR
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amdvi_page_fault(uint64_t addr) "error: page fault accessing guest physical address 0x%"PRIx64
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amdvi_iotlb_hit(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "hit iotlb devid %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64
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amdvi_translation_result(uint8_t bus, uint8_t slot, uint8_t func, uint64_t addr, uint64_t txaddr) "devid: %02x:%02x.%x gpa 0x%"PRIx64" hpa 0x%"PRIx64
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amdvi_mem_ir_write_req(uint64_t addr, uint64_t val, uint32_t size) "addr 0x%"PRIx64" data 0x%"PRIx64" size 0x%"PRIx32
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amdvi_mem_ir_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" data 0x%"PRIx64
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amdvi_ir_remap_msi_req(uint64_t addr, uint64_t data, uint8_t devid) "addr 0x%"PRIx64" data 0x%"PRIx64" devid 0x%"PRIx8
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amdvi_ir_remap_msi(uint64_t addr, uint64_t data, uint64_t addr2, uint64_t data2) "(addr 0x%"PRIx64", data 0x%"PRIx64") -> (addr 0x%"PRIx64", data 0x%"PRIx64")"
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amdvi_err(const char *str) "%s"
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# hw/i386/vmport.c
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vmport_register(unsigned char command, void *func, void *opaque) "command: 0x%02x func: %p opaque: %p"
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