From 57c108b86461a050a58b1ca9d31fd6e4af32205c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= Date: Thu, 6 Jan 2022 22:01:01 +0100 Subject: [PATCH] target/riscv: support for 128-bit U-type instructions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adding the 128-bit version of lui and auipc, and introducing to that end a "set register with immediat" function to handle extension on 128 bits. Signed-off-by: Frédéric Pétrot Co-authored-by: Fabien Portas Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20220106210108.138226-12-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 8 ++++---- target/riscv/translate.c | 21 +++++++++++++++++++++ 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index e572976e88..6113acc669 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -26,14 +26,14 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a) static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a) { - REQUIRE_64BIT(ctx); - return trans_illegal(ctx, a); + REQUIRE_64_OR_128BIT(ctx); + return trans_illegal(ctx, a); } static bool trans_lui(DisasContext *ctx, arg_lui *a) { if (a->rd != 0) { - tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm); + gen_set_gpri(ctx, a->rd, a->imm); } return true; } @@ -41,7 +41,7 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a) static bool trans_auipc(DisasContext *ctx, arg_auipc *a) { if (a->rd != 0) { - tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next); + gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next); } return true; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b43efc9bc3..ba1ad1be5f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -322,6 +322,27 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) } } +static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) +{ + if (reg_num != 0) { + switch (get_ol(ctx)) { + case MXL_RV32: + tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); + break; + case MXL_RV64: + case MXL_RV128: + tcg_gen_movi_tl(cpu_gpr[reg_num], imm); + break; + default: + g_assert_not_reached(); + } + + if (get_xl_max(ctx) == MXL_RV128) { + tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); + } + } +} + static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) { assert(get_ol(ctx) == MXL_RV128);