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target/sh4: do not check for PR bit for fabs instruction 

The SH4 manual is not fully clear about that, but real hardware do not
check for the PR bit, which allows to select between single or double
precision, for the fabs instruction. This is probably what is meant by
"Same operation is performed regardless of precision."

Remove the check, and at the same time use a TCG instruction instead of
a helper to clear one bit.

LP: https://bugs.launchpad.net/qemu/+bug/1701821
Reported-by: Bruno Haible <bruno@clisp.org>
Message-Id: <20170702202814.27793-2-aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2017-07-02 18:18:14 +02:00
parent 6887dc6700
commit 57f5c1b093
3 changed files with 3 additions and 24 deletions
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2
target/sh4/helper.h
View File

@ -16,8 +16,6 @@ DEF_HELPER_3(macw, void, env, i32, i32)
DEF_HELPER_2(ld_fpscr, void, env, i32) DEF_HELPER_2(ld_fpscr, void, env, i32)
DEF_HELPER_FLAGS_1(fabs_FT, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_FLAGS_1(fabs_DT, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_FLAGS_3(fadd_FT, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fadd_FT, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fadd_DT, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fadd_DT, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_2(fcnvsd_FT_DT, TCG_CALL_NO_WG, f64, env, f32) DEF_HELPER_FLAGS_2(fcnvsd_FT_DT, TCG_CALL_NO_WG, f64, env, f32)

10
target/sh4/op_helper.c
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@ -252,16 +252,6 @@ static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
} }
} }
float32 helper_fabs_FT(float32 t0)
{
return float32_abs(t0);
}
float64 helper_fabs_DT(float64 t0)
{
return float64_abs(t0);
}
float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1) float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
{ {
set_float_exception_flags(0, &env->fp_status); set_float_exception_flags(0, &env->fp_status);

15
target/sh4/translate.c
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@ -1695,19 +1695,10 @@ static void _decode_opc(DisasContext * ctx)
gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
} }
return; return;
case 0xf05d: /* fabs FRn/DRn */ case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */
CHECK_FPU_ENABLED CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_PR) { tcg_gen_andi_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)],
if (ctx->opcode & 0x0100) 0x7fffffff);
break; /* illegal instruction */
TCGv_i64 fp = tcg_temp_new_i64();
gen_load_fpr64(fp, DREG(B11_8));
gen_helper_fabs_DT(fp, fp);
gen_store_fpr64(fp, DREG(B11_8));
tcg_temp_free_i64(fp);
} else {
gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
}
return; return;
case 0xf06d: /* fsqrt FRn */ case 0xf06d: /* fsqrt FRn */
CHECK_FPU_ENABLED CHECK_FPU_ENABLED