target/i386: implement VLDMXCSR/VSTMXCSR
These are exactly the same as the non-VEX version, but one has to be careful that only VEX.L=0 is allowed. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
892544317f
commit
57f6bba023
|
@ -82,6 +82,10 @@
|
|||
|
||||
#define X86_OP_ENTRY2(op, op0, s0, op1, s1, ...) \
|
||||
X86_OP_ENTRY3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__)
|
||||
#define X86_OP_ENTRYw(op, op0, s0, ...) \
|
||||
X86_OP_ENTRY3(op, op0, s0, None, None, None, None, ## __VA_ARGS__)
|
||||
#define X86_OP_ENTRYr(op, op0, s0, ...) \
|
||||
X86_OP_ENTRY3(op, None, None, None, None, op0, s0, ## __VA_ARGS__)
|
||||
#define X86_OP_ENTRY0(op, ...) \
|
||||
X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__)
|
||||
|
||||
|
@ -149,6 +153,25 @@ static inline const X86OpEntry *decode_by_prefix(DisasContext *s, const X86OpEnt
|
|||
}
|
||||
}
|
||||
|
||||
static void decode_group15(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
||||
{
|
||||
/* only includes ldmxcsr and stmxcsr, because they have AVX variants. */
|
||||
static const X86OpEntry group15_reg[8] = {
|
||||
};
|
||||
|
||||
static const X86OpEntry group15_mem[8] = {
|
||||
[2] = X86_OP_ENTRYr(LDMXCSR, E,d, vex5),
|
||||
[3] = X86_OP_ENTRYw(STMXCSR, E,d, vex5),
|
||||
};
|
||||
|
||||
uint8_t modrm = get_modrm(s, env);
|
||||
if ((modrm >> 6) == 3) {
|
||||
*entry = group15_reg[(modrm >> 3) & 7];
|
||||
} else {
|
||||
*entry = group15_mem[(modrm >> 3) & 7];
|
||||
}
|
||||
}
|
||||
|
||||
static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
|
||||
{
|
||||
static const X86GenFunc group17_gen[8] = {
|
||||
|
@ -830,6 +853,8 @@ static const X86OpEntry opcodes_0F[256] = {
|
|||
[0x7e] = X86_OP_GROUP0(0F7E),
|
||||
[0x7f] = X86_OP_GROUP0(0F7F),
|
||||
|
||||
[0xae] = X86_OP_GROUP0(group15),
|
||||
|
||||
[0xc2] = X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2),
|
||||
[0xc4] = X86_OP_ENTRY4(PINSRW, V,dq,H,dq,E,w, vex5 mmx p_00_66),
|
||||
[0xc5] = X86_OP_ENTRY3(PEXTRW, G,d, U,dq,I,b, vex5 mmx p_00_66),
|
||||
|
|
|
@ -1099,6 +1099,16 @@ static void gen_INSERTQ_r(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec
|
|||
gen_helper_insertq_r(cpu_env, OP_PTR0, OP_PTR2);
|
||||
}
|
||||
|
||||
static void gen_LDMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
|
||||
{
|
||||
if (s->vex_l) {
|
||||
gen_illegal_opcode(s);
|
||||
return;
|
||||
}
|
||||
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T1);
|
||||
gen_helper_ldmxcsr(cpu_env, s->tmp2_i32);
|
||||
}
|
||||
|
||||
static void gen_MASKMOV(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
|
||||
{
|
||||
tcg_gen_mov_tl(s->A0, cpu_regs[R_EDI]);
|
||||
|
@ -1688,6 +1698,16 @@ static void gen_VAESKEYGEN(DisasContext *s, CPUX86State *env, X86DecodedInsn *de
|
|||
gen_helper_aeskeygenassist_xmm(cpu_env, OP_PTR0, OP_PTR1, imm);
|
||||
}
|
||||
|
||||
static void gen_STMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
|
||||
{
|
||||
if (s->vex_l) {
|
||||
gen_illegal_opcode(s);
|
||||
return;
|
||||
}
|
||||
gen_helper_update_mxcsr(cpu_env);
|
||||
tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, mxcsr));
|
||||
}
|
||||
|
||||
static void gen_VAESIMC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
|
||||
{
|
||||
assert(!s->vex_l);
|
||||
|
|
Loading…
Reference in New Issue