target-arm: Move feature bit settings to CPU init fns
Move the setting of the feature bits from cpu_reset_model_id() to each CPU's instance init function. This requires us to move the features field in CPUARMState so that it is not cleared on reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
parent
777dc78411
commit
581be09434
@ -79,5 +79,6 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
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#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
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void arm_cpu_realize(ARMCPU *cpu);
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#endif
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132
target-arm/cpu.c
132
target-arm/cpu.c
@ -34,6 +34,11 @@ static void arm_cpu_reset(CPUState *s)
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cpu_state_reset(&cpu->env);
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}
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static inline void set_feature(CPUARMState *env, int feature)
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{
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env->features |= 1u << feature;
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}
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static void arm_cpu_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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@ -41,161 +46,288 @@ static void arm_cpu_initfn(Object *obj)
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cpu_exec_init(&cpu->env);
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}
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void arm_cpu_realize(ARMCPU *cpu)
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{
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/* This function is called by cpu_arm_init() because it
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* needs to do common actions based on feature bits, etc
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* that have been set by the subclass init functions.
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* When we have QOM realize support it should become
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* a true realize function instead.
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*/
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CPUARMState *env = &cpu->env;
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V7)) {
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set_feature(env, ARM_FEATURE_VAPA);
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set_feature(env, ARM_FEATURE_THUMB2);
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_V6K);
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} else {
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set_feature(env, ARM_FEATURE_V6);
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}
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}
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if (arm_feature(env, ARM_FEATURE_V6K)) {
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set_feature(env, ARM_FEATURE_V6);
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set_feature(env, ARM_FEATURE_MVFR);
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}
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if (arm_feature(env, ARM_FEATURE_V6)) {
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set_feature(env, ARM_FEATURE_V5);
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_AUXCR);
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}
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}
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if (arm_feature(env, ARM_FEATURE_V5)) {
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set_feature(env, ARM_FEATURE_V4T);
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}
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if (arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV);
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}
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if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV);
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}
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if (arm_feature(env, ARM_FEATURE_VFP4)) {
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set_feature(env, ARM_FEATURE_VFP3);
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}
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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set_feature(env, ARM_FEATURE_VFP);
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}
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}
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/* CPU models */
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static void arm926_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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cpu->midr = ARM_CPUID_ARM926;
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}
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static void arm946_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_MPU);
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cpu->midr = ARM_CPUID_ARM946;
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}
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static void arm1026_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_AUXCR);
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cpu->midr = ARM_CPUID_ARM1026;
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}
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static void arm1136_r2_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V6);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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cpu->midr = ARM_CPUID_ARM1136_R2;
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}
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static void arm1136_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V6K);
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set_feature(&cpu->env, ARM_FEATURE_V6);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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cpu->midr = ARM_CPUID_ARM1136;
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}
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static void arm1176_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V6K);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_VAPA);
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cpu->midr = ARM_CPUID_ARM1176;
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}
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static void arm11mpcore_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V6K);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_VAPA);
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cpu->midr = ARM_CPUID_ARM11MPCORE;
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}
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static void cortex_m3_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_M);
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cpu->midr = ARM_CPUID_CORTEXM3;
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}
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static void cortex_a8_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_VFP3);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
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cpu->midr = ARM_CPUID_CORTEXA8;
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}
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static void cortex_a9_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_VFP3);
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set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
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/* Note that A9 supports the MP extensions even for
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* A9UP and single-core A9MP (which are both different
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* and valid configurations; we don't model A9UP).
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*/
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set_feature(&cpu->env, ARM_FEATURE_V7MP);
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cpu->midr = ARM_CPUID_CORTEXA9;
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}
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static void cortex_a15_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
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set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
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set_feature(&cpu->env, ARM_FEATURE_V7MP);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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cpu->midr = ARM_CPUID_CORTEXA15;
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}
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static void ti925t_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V4T);
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set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
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cpu->midr = ARM_CPUID_TI925T;
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}
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static void sa1100_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
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cpu->midr = ARM_CPUID_SA1100;
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}
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static void sa1110_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
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cpu->midr = ARM_CPUID_SA1110;
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}
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static void pxa250_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA250;
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}
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static void pxa255_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA255;
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}
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static void pxa260_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA260;
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}
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static void pxa261_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA261;
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}
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static void pxa262_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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cpu->midr = ARM_CPUID_PXA262;
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}
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static void pxa270a0_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_A0;
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}
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static void pxa270a1_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_A1;
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}
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static void pxa270b0_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_B0;
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}
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static void pxa270b1_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_B1;
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}
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static void pxa270c0_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_C0;
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}
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static void pxa270c5_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_XSCALE);
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set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
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cpu->midr = ARM_CPUID_PXA270_C5;
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}
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static void arm_any_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
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set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
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set_feature(&cpu->env, ARM_FEATURE_V7MP);
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cpu->midr = ARM_CPUID_ANY;
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}
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@ -170,9 +170,6 @@ typedef struct CPUARMState {
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uint32_t teecr;
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uint32_t teehbr;
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/* Internal CPU feature flags. */
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uint32_t features;
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/* VFP coprocessor state. */
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struct {
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float64 regs[32];
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@ -228,6 +225,9 @@ typedef struct CPUARMState {
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/* These fields after the common ones so they are preserved on reset. */
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/* Internal CPU feature flags. */
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uint32_t features;
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/* Coprocessor IO used by peripherals */
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struct {
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ARMReadCPFunc *cp_read;
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@ -46,46 +46,30 @@ static uint32_t arm1176_cp15_c0_c1[8] =
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static uint32_t arm1176_cp15_c0_c2[8] =
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{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
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static inline void set_feature(CPUARMState *env, int feature)
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{
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env->features |= 1u << feature;
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}
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static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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{
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switch (id) {
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case ARM_CPUID_ARM926:
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set_feature(env, ARM_FEATURE_V5);
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set_feature(env, ARM_FEATURE_VFP);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00090078;
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break;
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case ARM_CPUID_ARM946:
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set_feature(env, ARM_FEATURE_V5);
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set_feature(env, ARM_FEATURE_MPU);
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env->cp15.c0_cachetype = 0x0f004006;
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env->cp15.c1_sys = 0x00000078;
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break;
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case ARM_CPUID_ARM1026:
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set_feature(env, ARM_FEATURE_V5);
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set_feature(env, ARM_FEATURE_VFP);
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set_feature(env, ARM_FEATURE_AUXCR);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00090078;
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break;
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case ARM_CPUID_ARM1136:
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/* This is the 1136 r1, which is a v6K core */
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set_feature(env, ARM_FEATURE_V6K);
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/* Fall through */
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case ARM_CPUID_ARM1136_R2:
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/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
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* older core than plain "arm1136". In particular this does not
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* have the v6K features.
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*/
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set_feature(env, ARM_FEATURE_V6);
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set_feature(env, ARM_FEATURE_VFP);
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/* These ID register values are correct for 1136 but may be wrong
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* for 1136_r2 (in particular r0p2 does not actually implement most
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* of the ID registers).
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@ -99,9 +83,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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env->cp15.c1_sys = 0x00050078;
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break;
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case ARM_CPUID_ARM1176:
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set_feature(env, ARM_FEATURE_V6K);
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set_feature(env, ARM_FEATURE_VFP);
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set_feature(env, ARM_FEATURE_VAPA);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
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@ -111,9 +92,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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env->cp15.c1_sys = 0x00050078;
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break;
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case ARM_CPUID_ARM11MPCORE:
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set_feature(env, ARM_FEATURE_V6K);
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set_feature(env, ARM_FEATURE_VFP);
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set_feature(env, ARM_FEATURE_VAPA);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
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@ -122,10 +100,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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env->cp15.c0_cachetype = 0x1dd20d2;
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break;
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case ARM_CPUID_CORTEXA8:
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set_feature(env, ARM_FEATURE_V7);
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set_feature(env, ARM_FEATURE_VFP3);
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set_feature(env, ARM_FEATURE_NEON);
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set_feature(env, ARM_FEATURE_THUMB2EE);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
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env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
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env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
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@ -139,16 +113,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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env->cp15.c1_sys = 0x00c50078;
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break;
|
||||
case ARM_CPUID_CORTEXA9:
|
||||
set_feature(env, ARM_FEATURE_V7);
|
||||
set_feature(env, ARM_FEATURE_VFP3);
|
||||
set_feature(env, ARM_FEATURE_VFP_FP16);
|
||||
set_feature(env, ARM_FEATURE_NEON);
|
||||
set_feature(env, ARM_FEATURE_THUMB2EE);
|
||||
/* Note that A9 supports the MP extensions even for
|
||||
* A9UP and single-core A9MP (which are both different
|
||||
* and valid configurations; we don't model A9UP).
|
||||
*/
|
||||
set_feature(env, ARM_FEATURE_V7MP);
|
||||
env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
|
||||
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
|
||||
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
|
||||
@ -161,14 +125,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
env->cp15.c1_sys = 0x00c50078;
|
||||
break;
|
||||
case ARM_CPUID_CORTEXA15:
|
||||
set_feature(env, ARM_FEATURE_V7);
|
||||
set_feature(env, ARM_FEATURE_VFP4);
|
||||
set_feature(env, ARM_FEATURE_VFP_FP16);
|
||||
set_feature(env, ARM_FEATURE_NEON);
|
||||
set_feature(env, ARM_FEATURE_THUMB2EE);
|
||||
set_feature(env, ARM_FEATURE_ARM_DIV);
|
||||
set_feature(env, ARM_FEATURE_V7MP);
|
||||
set_feature(env, ARM_FEATURE_GENERIC_TIMER);
|
||||
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
|
||||
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
|
||||
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
|
||||
@ -182,22 +138,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
env->cp15.c1_sys = 0x00c50078;
|
||||
break;
|
||||
case ARM_CPUID_CORTEXM3:
|
||||
set_feature(env, ARM_FEATURE_V7);
|
||||
set_feature(env, ARM_FEATURE_M);
|
||||
break;
|
||||
case ARM_CPUID_ANY: /* For userspace emulation. */
|
||||
set_feature(env, ARM_FEATURE_V7);
|
||||
set_feature(env, ARM_FEATURE_VFP4);
|
||||
set_feature(env, ARM_FEATURE_VFP_FP16);
|
||||
set_feature(env, ARM_FEATURE_NEON);
|
||||
set_feature(env, ARM_FEATURE_THUMB2EE);
|
||||
set_feature(env, ARM_FEATURE_ARM_DIV);
|
||||
set_feature(env, ARM_FEATURE_V7MP);
|
||||
break;
|
||||
case ARM_CPUID_TI915T:
|
||||
case ARM_CPUID_TI925T:
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
set_feature(env, ARM_FEATURE_OMAPCP);
|
||||
env->cp15.c0_cachetype = 0x5109149;
|
||||
env->cp15.c1_sys = 0x00000070;
|
||||
env->cp15.c15_i_max = 0x000;
|
||||
@ -208,8 +153,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
case ARM_CPUID_PXA260:
|
||||
case ARM_CPUID_PXA261:
|
||||
case ARM_CPUID_PXA262:
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_XSCALE);
|
||||
/* JTAG_ID is ((id << 28) | 0x09265013) */
|
||||
env->cp15.c0_cachetype = 0xd172172;
|
||||
env->cp15.c1_sys = 0x00000078;
|
||||
@ -220,17 +163,13 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
case ARM_CPUID_PXA270_B1:
|
||||
case ARM_CPUID_PXA270_C0:
|
||||
case ARM_CPUID_PXA270_C5:
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
set_feature(env, ARM_FEATURE_XSCALE);
|
||||
/* JTAG_ID is ((id << 28) | 0x09265013) */
|
||||
set_feature(env, ARM_FEATURE_IWMMXT);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
|
||||
env->cp15.c0_cachetype = 0xd172172;
|
||||
env->cp15.c1_sys = 0x00000078;
|
||||
break;
|
||||
case ARM_CPUID_SA1100:
|
||||
case ARM_CPUID_SA1110:
|
||||
set_feature(env, ARM_FEATURE_STRONGARM);
|
||||
env->cp15.c1_sys = 0x00000070;
|
||||
break;
|
||||
default:
|
||||
@ -238,41 +177,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
|
||||
break;
|
||||
}
|
||||
|
||||
/* Some features automatically imply others: */
|
||||
if (arm_feature(env, ARM_FEATURE_V7)) {
|
||||
set_feature(env, ARM_FEATURE_VAPA);
|
||||
set_feature(env, ARM_FEATURE_THUMB2);
|
||||
if (!arm_feature(env, ARM_FEATURE_M)) {
|
||||
set_feature(env, ARM_FEATURE_V6K);
|
||||
} else {
|
||||
set_feature(env, ARM_FEATURE_V6);
|
||||
}
|
||||
}
|
||||
if (arm_feature(env, ARM_FEATURE_V6K)) {
|
||||
set_feature(env, ARM_FEATURE_V6);
|
||||
set_feature(env, ARM_FEATURE_MVFR);
|
||||
}
|
||||
if (arm_feature(env, ARM_FEATURE_V6)) {
|
||||
set_feature(env, ARM_FEATURE_V5);
|
||||
if (!arm_feature(env, ARM_FEATURE_M)) {
|
||||
set_feature(env, ARM_FEATURE_AUXCR);
|
||||
}
|
||||
}
|
||||
if (arm_feature(env, ARM_FEATURE_V5)) {
|
||||
set_feature(env, ARM_FEATURE_V4T);
|
||||
}
|
||||
if (arm_feature(env, ARM_FEATURE_M)) {
|
||||
set_feature(env, ARM_FEATURE_THUMB_DIV);
|
||||
}
|
||||
if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
|
||||
set_feature(env, ARM_FEATURE_THUMB_DIV);
|
||||
}
|
||||
if (arm_feature(env, ARM_FEATURE_VFP4)) {
|
||||
set_feature(env, ARM_FEATURE_VFP3);
|
||||
}
|
||||
if (arm_feature(env, ARM_FEATURE_VFP3)) {
|
||||
set_feature(env, ARM_FEATURE_VFP);
|
||||
}
|
||||
}
|
||||
|
||||
/* TODO Move contents into arm_cpu_reset() in cpu.c,
|
||||
@ -413,6 +317,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
|
||||
cpu = ARM_CPU(object_new(cpu_model));
|
||||
env = &cpu->env;
|
||||
env->cpu_model_str = cpu_model;
|
||||
arm_cpu_realize(cpu);
|
||||
|
||||
if (tcg_enabled() && !inited) {
|
||||
inited = 1;
|
||||
|
Loading…
Reference in New Issue
Block a user