tcg: Add flags argument to bswap opcodes
This will eventually simplify front-end usage, and will allow backends to unset TCG_TARGET_HAS_MEMORY_BSWAP without loss of optimization. The argument is added during expansion, not currently exposed to the front end translators. The backends currently only support a flags value of either TCG_BSWAP_IZ, or (TCG_BSWAP_IZ | TCG_BSWAP_OZ), since they all require zero top bytes and leave them that way. At the existing call sites we pass in (TCG_BSWAP_IZ | TCG_BSWAP_OZ), except for the flags-ignored cases of a 32-bit swap of a 32-bit value and or a 64-bit swap of a 64-bit value, where we pass 0. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
4f862f79ca
commit
587195bd59
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@ -96,8 +96,8 @@ DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
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DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
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DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
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DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
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DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
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DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
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DEF(bswap16_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap16_i32))
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DEF(bswap32_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap32_i32))
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DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
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DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
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DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
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@ -165,9 +165,9 @@ DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
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DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
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DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
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DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
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DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
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DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
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DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
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DEF(bswap16_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
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DEF(bswap32_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
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DEF(bswap64_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
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DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
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DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
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DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
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@ -408,6 +408,18 @@ typedef TCGv_ptr TCGv_env;
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/* Used to align parameters. See the comment before tcgv_i32_temp. */
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#define TCG_CALL_DUMMY_ARG ((TCGArg)0)
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/*
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* Flags for the bswap opcodes.
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* If IZ, the input is zero-extended, otherwise unknown.
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* If OZ or OS, the output is zero- or sign-extended respectively,
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* otherwise the high bits are undefined.
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*/
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enum {
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TCG_BSWAP_IZ = 1,
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TCG_BSWAP_OZ = 2,
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TCG_BSWAP_OS = 4,
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};
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typedef enum TCGTempVal {
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TEMP_VAL_DEAD,
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TEMP_VAL_REG,
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22
tcg/README
22
tcg/README
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@ -295,19 +295,25 @@ ext32u_i64 t0, t1
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8, 16 or 32 bit sign/zero extension (both operands must have the same type)
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* bswap16_i32/i64 t0, t1
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* bswap16_i32/i64 t0, t1, flags
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16 bit byte swap on a 32/64 bit value. It assumes that the two/six high order
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bytes are set to zero.
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16 bit byte swap on the low bits of a 32/64 bit input.
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If flags & TCG_BSWAP_IZ, then t1 is known to be zero-extended from bit 15.
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If flags & TCG_BSWAP_OZ, then t0 will be zero-extended from bit 15.
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If flags & TCG_BSWAP_OS, then t0 will be sign-extended from bit 15.
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If neither TCG_BSWAP_OZ nor TCG_BSWAP_OS are set, then the bits of
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t0 above bit 15 may contain any value.
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* bswap32_i32/i64 t0, t1
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* bswap32_i64 t0, t1, flags
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32 bit byte swap on a 32/64 bit value. With a 64 bit value, it assumes that
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the four high order bytes are set to zero.
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32 bit byte swap on a 64-bit value. The flags are the same as for bswap16,
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except they apply from bit 31 instead of bit 15.
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* bswap64_i64 t0, t1
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* bswap32_i32 t0, t1, flags
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* bswap64_i64 t0, t1, flags
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64 bit byte swap
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32/64 bit byte swap. The flags are ignored, but still present
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for consistency with the other bswap opcodes.
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* discard_i32/i64 t0
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13
tcg/tcg-op.c
13
tcg/tcg-op.c
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@ -1005,7 +1005,8 @@ void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
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void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
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{
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if (TCG_TARGET_HAS_bswap16_i32) {
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tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
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tcg_gen_op3i_i32(INDEX_op_bswap16_i32, ret, arg,
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TCG_BSWAP_IZ | TCG_BSWAP_OZ);
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} else {
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TCGv_i32 t0 = tcg_temp_new_i32();
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@ -1020,7 +1021,7 @@ void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
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void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
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{
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if (TCG_TARGET_HAS_bswap32_i32) {
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tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
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tcg_gen_op3i_i32(INDEX_op_bswap32_i32, ret, arg, 0);
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} else {
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i32 t1 = tcg_temp_new_i32();
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@ -1661,7 +1662,8 @@ void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
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tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
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tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
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} else if (TCG_TARGET_HAS_bswap16_i64) {
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tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
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tcg_gen_op3i_i64(INDEX_op_bswap16_i64, ret, arg,
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TCG_BSWAP_IZ | TCG_BSWAP_OZ);
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} else {
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TCGv_i64 t0 = tcg_temp_new_i64();
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@ -1680,7 +1682,8 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
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tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
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tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
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} else if (TCG_TARGET_HAS_bswap32_i64) {
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tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
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tcg_gen_op3i_i64(INDEX_op_bswap32_i64, ret, arg,
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TCG_BSWAP_IZ | TCG_BSWAP_OZ);
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} else {
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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@ -1717,7 +1720,7 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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} else if (TCG_TARGET_HAS_bswap64_i64) {
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tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
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tcg_gen_op3i_i64(INDEX_op_bswap64_i64, ret, arg, 0);
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} else {
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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28
tcg/tcg.c
28
tcg/tcg.c
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@ -1778,6 +1778,14 @@ static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = {
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[MO_ALIGN_64 >> MO_ASHIFT] = "al64+",
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};
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static const char bswap_flag_name[][6] = {
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[TCG_BSWAP_IZ] = "iz",
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[TCG_BSWAP_OZ] = "oz",
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[TCG_BSWAP_OS] = "os",
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[TCG_BSWAP_IZ | TCG_BSWAP_OZ] = "iz,oz",
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[TCG_BSWAP_IZ | TCG_BSWAP_OS] = "iz,os",
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};
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static inline bool tcg_regset_single(TCGRegSet d)
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{
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return (d & (d - 1)) == 0;
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@ -1921,6 +1929,26 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
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i = 1;
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}
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break;
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case INDEX_op_bswap16_i32:
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case INDEX_op_bswap16_i64:
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case INDEX_op_bswap32_i32:
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case INDEX_op_bswap32_i64:
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case INDEX_op_bswap64_i64:
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{
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TCGArg flags = op->args[k];
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const char *name = NULL;
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if (flags < ARRAY_SIZE(bswap_flag_name)) {
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name = bswap_flag_name[flags];
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}
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if (name) {
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col += qemu_log(",%s", name);
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} else {
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col += qemu_log(",$0x%" TCG_PRIlx, flags);
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}
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i = k = 1;
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}
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break;
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default:
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i = 0;
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break;
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