target-s390: Convert INSERT CHARACTERS UNDER MASK
Change the CC handling to be more like TEST UNDER MASK, with val & mask. This lets us handle ICMH much more like ICM. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
443aaeb899
commit
58a9e35bcc
@ -331,35 +331,18 @@ static uint32_t cc_calc_comp_32(int32_t dst)
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}
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/* calculate condition code for insert character under mask insn */
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static uint32_t cc_calc_icm_32(uint32_t mask, uint32_t val)
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static uint32_t cc_calc_icm(uint64_t mask, uint64_t val)
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{
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uint32_t cc;
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HELPER_LOG("%s: mask 0x%x val %d\n", __func__, mask, val);
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if (mask == 0xf) {
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if (!val) {
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return 0;
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} else if (val & 0x80000000) {
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if ((val & mask) == 0) {
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return 0;
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} else {
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int top = clz64(mask);
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if ((int64_t)(val << top) < 0) {
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return 1;
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} else {
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return 2;
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}
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}
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if (!val || !mask) {
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cc = 0;
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} else {
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while (mask != 1) {
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mask >>= 1;
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val >>= 8;
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}
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if (val & 0x80) {
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cc = 1;
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} else {
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cc = 2;
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}
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}
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return cc;
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}
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static uint32_t cc_calc_slag(uint64_t src, uint64_t shift)
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@ -488,7 +471,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
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break;
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case CC_OP_ICM:
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r = cc_calc_icm_32(src, dst);
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r = cc_calc_icm(src, dst);
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break;
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case CC_OP_SLAG:
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r = cc_calc_slag(src, dst);
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@ -27,7 +27,6 @@ DEF_HELPER_FLAGS_1(nabs_i32, TCG_CALL_NO_RWG_SE, s32, s32)
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DEF_HELPER_FLAGS_1(abs_i64, TCG_CALL_NO_RWG_SE, i64, s64)
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DEF_HELPER_FLAGS_1(nabs_i64, TCG_CALL_NO_RWG_SE, s64, s64)
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DEF_HELPER_4(stcmh, void, env, i32, i64, i32)
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DEF_HELPER_4(icmh, i32, env, i32, i64, i32)
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DEF_HELPER_3(ipm, void, env, i32, i32)
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DEF_HELPER_4(stam, void, env, i32, i64, i32)
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DEF_HELPER_4(lam, void, env, i32, i64, i32)
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@ -160,6 +160,10 @@
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/* INSERT CHARACTER */
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C(0x4300, IC, RX_a, Z, 0, m2_8u, 0, r1_8, mov2, 0)
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C(0xe373, ICY, RXY_a, LD, 0, m2_8u, 0, r1_8, mov2, 0)
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/* INSERT CHARACTERS UNDER MASK */
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D(0xbf00, ICM, RS_b, Z, 0, a2, r1, 0, icm, 0, 0)
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D(0xeb81, ICMY, RSY_b, LD, 0, a2, r1, 0, icm, 0, 0)
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D(0xeb80, ICMH, RSY_b, Z, 0, a2, r1, 0, icm, 0, 32)
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/* INSERT IMMEDIATE */
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D(0xc008, IIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2020)
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D(0xc009, IILF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2000)
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@ -629,39 +629,6 @@ void HELPER(stcmh)(CPUS390XState *env, uint32_t r1, uint64_t address,
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}
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}
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/* insert character under mask high; same as icm, but operates on the
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upper half of r1 */
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uint32_t HELPER(icmh)(CPUS390XState *env, uint32_t r1, uint64_t address,
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uint32_t mask)
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{
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int pos = 56; /* top of the upper half of r1 */
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uint64_t rmask = 0xff00000000000000ULL;
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uint8_t val = 0;
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int ccd = 0;
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uint32_t cc = 0;
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while (mask) {
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if (mask & 8) {
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env->regs[r1] &= ~rmask;
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val = cpu_ldub_data(env, address);
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if ((val & 0x80) && !ccd) {
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cc = 1;
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}
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ccd = 1;
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if (val && cc == 0) {
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cc = 2;
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}
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env->regs[r1] |= (uint64_t)val << pos;
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address++;
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}
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mask = (mask << 1) & 0xf;
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pos -= 8;
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rmask >>= 8;
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}
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return cc;
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}
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/* load access registers r1 to r3 from memory at a2 */
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void HELPER(lam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
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{
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@ -32,6 +32,7 @@
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#include "disas/disas.h"
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#include "tcg-op.h"
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#include "qemu/log.h"
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#include "qemu/host-utils.h"
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/* global register indexes */
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static TCGv_ptr cpu_env;
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@ -561,11 +562,6 @@ static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
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gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
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}
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static void set_cc_icm(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
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{
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gen_op_update2_cc_i32(s, CC_OP_ICM, v1, v2);
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}
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static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2)
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{
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tcg_gen_extu_i32_i64(cc_src, v1);
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@ -896,7 +892,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
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case CC_OP_LTGT0_64:
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case CC_OP_NZ:
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case CC_OP_ICM:
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c->u.s64.a = cc_dst;
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c->u.s64.b = tcg_const_i64(0);
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c->g1 = true;
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@ -910,6 +905,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
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case CC_OP_TM_32:
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case CC_OP_TM_64:
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case CC_OP_ICM:
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c->u.s64.a = tcg_temp_new_i64();
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c->u.s64.b = tcg_const_i64(0);
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tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
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@ -1521,18 +1517,6 @@ do_mh:
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tcg_temp_free_i64(tmp);
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tcg_temp_free_i64(tmp2);
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break;
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case 0x80: /* ICMH R1,M3,D2(B2) [RSY] */
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tmp = get_address(s, 0, b2, d2);
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tmp32_1 = tcg_const_i32(r1);
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tmp32_2 = tcg_const_i32(r3);
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potential_page_fault(s);
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/* XXX split CC calculation out */
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gen_helper_icmh(cc_op, cpu_env, tmp32_1, tmp, tmp32_2);
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set_cc_static(s);
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tcg_temp_free_i64(tmp);
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tcg_temp_free_i32(tmp32_1);
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tcg_temp_free_i32(tmp32_2);
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break;
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default:
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LOG_DISAS("illegal eb operation 0x%x\n", op);
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gen_illegal_opcode(s);
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@ -2361,7 +2345,7 @@ static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1,
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static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
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{
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TCGv_i64 tmp, tmp2, tmp3, tmp4;
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TCGv_i32 tmp32_1, tmp32_2, tmp32_3, tmp32_4;
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TCGv_i32 tmp32_1, tmp32_2;
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unsigned char opc;
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uint64_t insn;
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int op, r1, r2, r3, d1, d2, x2, b1, b2, i, i2, r1b;
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@ -2786,60 +2770,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
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tcg_temp_free_i32(tmp32_1);
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tcg_temp_free_i32(tmp32_2);
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break;
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case 0xbf: /* ICM R1,M3,D2(B2) [RS] */
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insn = ld_code4(env, s->pc);
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decode_rs(s, insn, &r1, &r3, &b2, &d2);
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if (r3 == 15) {
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/* effectively a 32-bit load */
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tmp = get_address(s, 0, b2, d2);
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tmp32_1 = tcg_temp_new_i32();
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tmp32_2 = tcg_const_i32(r3);
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tcg_gen_qemu_ld32u(tmp, tmp, get_mem_index(s));
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store_reg32_i64(r1, tmp);
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tcg_gen_trunc_i64_i32(tmp32_1, tmp);
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set_cc_icm(s, tmp32_2, tmp32_1);
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tcg_temp_free_i64(tmp);
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tcg_temp_free_i32(tmp32_1);
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tcg_temp_free_i32(tmp32_2);
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} else if (r3) {
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uint32_t mask = 0x00ffffffUL;
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uint32_t shift = 24;
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int m3 = r3;
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tmp = get_address(s, 0, b2, d2);
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tmp2 = tcg_temp_new_i64();
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tmp32_1 = load_reg32(r1);
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tmp32_2 = tcg_temp_new_i32();
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tmp32_3 = tcg_const_i32(r3);
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tmp32_4 = tcg_const_i32(0);
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while (m3) {
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if (m3 & 8) {
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tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
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tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
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if (shift) {
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tcg_gen_shli_i32(tmp32_2, tmp32_2, shift);
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}
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tcg_gen_andi_i32(tmp32_1, tmp32_1, mask);
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tcg_gen_or_i32(tmp32_1, tmp32_1, tmp32_2);
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tcg_gen_or_i32(tmp32_4, tmp32_4, tmp32_2);
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tcg_gen_addi_i64(tmp, tmp, 1);
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}
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m3 = (m3 << 1) & 0xf;
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mask = (mask >> 8) | 0xff000000UL;
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shift -= 8;
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}
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store_reg32(r1, tmp32_1);
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set_cc_icm(s, tmp32_3, tmp32_4);
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tcg_temp_free_i64(tmp);
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tcg_temp_free_i64(tmp2);
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tcg_temp_free_i32(tmp32_1);
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tcg_temp_free_i32(tmp32_2);
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tcg_temp_free_i32(tmp32_3);
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tcg_temp_free_i32(tmp32_4);
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} else {
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/* i.e. env->cc = 0 */
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gen_op_movi_cc(s, 0);
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}
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break;
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case 0xd2: /* MVC D1(L,B1),D2(B2) [SS] */
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case 0xd4: /* NC D1(L,B1),D2(B2) [SS] */
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case 0xd5: /* CLC D1(L,B1),D2(B2) [SS] */
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@ -3493,6 +3423,66 @@ static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
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return NO_EXIT;
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}
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static ExitStatus op_icm(DisasContext *s, DisasOps *o)
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{
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int m3 = get_field(s->fields, m3);
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int pos, len, base = s->insn->data;
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TCGv_i64 tmp = tcg_temp_new_i64();
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uint64_t ccm;
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switch (m3) {
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case 0xf:
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/* Effectively a 32-bit load. */
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tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
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len = 32;
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goto one_insert;
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case 0xc:
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case 0x6:
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case 0x3:
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/* Effectively a 16-bit load. */
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tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
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len = 16;
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goto one_insert;
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case 0x8:
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case 0x4:
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case 0x2:
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case 0x1:
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/* Effectively an 8-bit load. */
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tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
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len = 8;
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goto one_insert;
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one_insert:
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pos = base + ctz32(m3) * 8;
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tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
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ccm = ((1ull << len) - 1) << pos;
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break;
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default:
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/* This is going to be a sequence of loads and inserts. */
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pos = base + 32 - 8;
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ccm = 0;
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while (m3) {
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if (m3 & 0x8) {
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tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
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tcg_gen_addi_i64(o->in2, o->in2, 1);
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tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
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ccm |= 0xff << pos;
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}
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m3 = (m3 << 1) & 0xf;
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pos -= 8;
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}
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break;
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}
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tcg_gen_movi_i64(tmp, ccm);
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gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
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tcg_temp_free_i64(tmp);
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return NO_EXIT;
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}
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static ExitStatus op_insi(DisasContext *s, DisasOps *o)
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{
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int shift = s->insn->data & 0xff;
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