target-alpha: Implement cvtlq inline.
It's a simple shift and mask sequence. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -83,7 +83,6 @@ DEF_HELPER_FLAGS_1(cvtqf, TCG_CALL_CONST, i64, i64)
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DEF_HELPER_FLAGS_1(cvtgf, TCG_CALL_CONST, i64, i64)
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DEF_HELPER_FLAGS_1(cvtgq, TCG_CALL_CONST, i64, i64)
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DEF_HELPER_FLAGS_1(cvtqg, TCG_CALL_CONST, i64, i64)
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DEF_HELPER_FLAGS_1(cvtlq, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64)
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DEF_HELPER_FLAGS_1(cvttq, TCG_CALL_CONST, i64, i64)
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DEF_HELPER_FLAGS_1(cvttq_c, TCG_CALL_CONST, i64, i64)
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@ -1152,13 +1152,6 @@ uint64_t helper_cvtqg (uint64_t a)
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return float64_to_g(fr);
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}
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uint64_t helper_cvtlq (uint64_t a)
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{
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int32_t lo = a >> 29;
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int32_t hi = a >> 32;
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return (lo & 0x3FFFFFFF) | (hi & 0xc0000000);
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}
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/* PALcode support special instructions */
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#if !defined (CONFIG_USER_ONLY)
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void helper_hw_rei (void)
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@ -598,6 +598,28 @@ static inline void gen_fp_exc_raise(int rc, int fn11)
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gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact);
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}
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static void gen_fcvtlq(int rb, int rc)
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{
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if (unlikely(rc == 31)) {
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return;
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}
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if (unlikely(rb == 31)) {
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tcg_gen_movi_i64(cpu_fir[rc], 0);
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} else {
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TCGv tmp = tcg_temp_new();
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/* The arithmetic right shift here, plus the sign-extended mask below
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yields a sign-extended result without an explicit ext32s_i64. */
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tcg_gen_sari_i64(tmp, cpu_fir[rb], 32);
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tcg_gen_shri_i64(cpu_fir[rc], cpu_fir[rb], 29);
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tcg_gen_andi_i64(tmp, tmp, (int32_t)0xc0000000);
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tcg_gen_andi_i64(cpu_fir[rc], cpu_fir[rc], 0x3fffffff);
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tcg_gen_or_i64(cpu_fir[rc], cpu_fir[rc], tmp);
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tcg_temp_free(tmp);
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}
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}
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static void gen_fcvtql(int rb, int rc)
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{
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if (unlikely(rc == 31)) {
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@ -647,7 +669,6 @@ static inline void glue(gen_f, name)(int rb, int rc) \
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tcg_temp_free(tmp); \
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} \
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}
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FARITH2(cvtlq)
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/* ??? VAX instruction qualifiers ignored. */
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FARITH2(sqrtf)
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