tcg/ppc: Change TCG_REG_RA to TCG_REG_TB
At this point the conversion is a wash. Loading of TB+ofs is smaller, but the actual return address from exit_tb is larger. There are a few more insns required to transition between TBs. But the expectation is that accesses to the constant pool will on the whole be smaller. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
afe74dbd6a
commit
5964fca8a1
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@ -39,29 +39,8 @@
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# define TCG_REG_TMP1 TCG_REG_R12
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#endif
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/* For the 64-bit target, we don't like the 5 insn sequence needed to build
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full 64-bit addresses. Better to have a base register to which we can
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apply a 32-bit displacement.
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There are generally three items of interest:
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(1) helper functions in the main executable,
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(2) TranslationBlock data structures,
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(3) the return address in the epilogue.
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For user-only, we USE_STATIC_CODE_GEN_BUFFER, so the code_gen_buffer
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will be inside the main executable, and thus near enough to make a
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pointer to the epilogue be within 2GB of all helper functions.
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For softmmu, we'll let the kernel choose the address of code_gen_buffer,
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and odds are it'll be somewhere close to the main malloc arena, and so
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a pointer to the epilogue will be within 2GB of the TranslationBlocks.
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For --enable-pie, everything will be kinda near everything else,
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somewhere in high memory.
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Thus we choose to keep the return address in a call-saved register. */
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#define TCG_REG_RA TCG_REG_R31
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#define USE_REG_RA (TCG_TARGET_REG_BITS == 64)
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#define TCG_REG_TB TCG_REG_R31
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#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
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/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
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#define SZP ((int)sizeof(void *))
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@ -614,50 +593,68 @@ static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
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tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
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}
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static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
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static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
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tcg_target_long arg, bool in_prologue)
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{
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if (arg == (int16_t) arg) {
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intptr_t tb_diff;
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int32_t high;
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tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
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if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
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arg = (int32_t)arg;
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}
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/* Load 16-bit immediates with one insn. */
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if (arg == (int16_t)arg) {
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tcg_out32(s, ADDI | TAI(ret, 0, arg));
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} else {
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return;
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}
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/* Load addresses within the TB with one insn. */
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tb_diff = arg - (intptr_t)s->code_gen_ptr;
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if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
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tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
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return;
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}
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/* Load 32-bit immediates with two insns. */
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if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
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tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
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if (arg & 0xffff) {
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tcg_out32(s, ORI | SAI(ret, ret, arg));
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}
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return;
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}
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if (arg == (uint32_t)arg && !(arg & 0x8000)) {
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tcg_out32(s, ADDI | TAI(ret, 0, arg));
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tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
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return;
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}
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/* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
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if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {
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tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);
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return;
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}
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high = arg >> 31 >> 1;
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tcg_out_movi(s, TCG_TYPE_I32, ret, high);
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if (high) {
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tcg_out_shli64(s, ret, ret, 32);
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}
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if (arg & 0xffff0000) {
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tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
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}
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if (arg & 0xffff) {
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tcg_out32(s, ORI | SAI(ret, ret, arg));
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}
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}
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static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
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tcg_target_long arg)
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static inline void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
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tcg_target_long arg)
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{
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tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
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if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
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tcg_out_movi32(s, ret, arg);
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} else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
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tcg_out32(s, ADDI | TAI(ret, 0, arg));
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tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
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} else {
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int32_t high;
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if (USE_REG_RA) {
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intptr_t diff = arg - (intptr_t)tb_ret_addr;
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if (diff == (int32_t)diff) {
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tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_RA, diff);
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return;
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}
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}
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high = arg >> 31 >> 1;
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tcg_out_movi32(s, ret, high);
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if (high) {
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tcg_out_shli64(s, ret, ret, 32);
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}
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if (arg & 0xffff0000) {
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tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
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}
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if (arg & 0xffff) {
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tcg_out32(s, ORI | SAI(ret, ret, arg));
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}
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}
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tcg_out_movi_int(s, type, ret, arg, false);
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}
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static bool mask_operand(uint32_t c, int *mb, int *me)
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@ -1293,49 +1290,43 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
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tcg_out32(s, insn);
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}
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#ifdef __powerpc64__
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void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
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uintptr_t addr)
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{
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tcg_insn_unit i1, i2;
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uint64_t pair;
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intptr_t diff = addr - jmp_addr;
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_insn_unit i1, i2;
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intptr_t tb_diff = addr - tc_ptr;
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intptr_t br_diff = addr - (jmp_addr + 4);
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uint64_t pair;
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if (in_range_b(diff)) {
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i1 = B | (diff & 0x3fffffc);
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i2 = NOP;
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} else if (USE_REG_RA) {
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intptr_t lo, hi;
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diff = addr - (uintptr_t)tb_ret_addr;
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lo = (int16_t)diff;
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hi = (int32_t)(diff - lo);
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tcg_debug_assert(diff == hi + lo);
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i1 = ADDIS | TAI(TCG_REG_TMP1, TCG_REG_RA, hi >> 16);
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i2 = ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, lo);
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} else {
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tcg_debug_assert(TCG_TARGET_REG_BITS == 32 || addr == (int32_t)addr);
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i1 = ADDIS | TAI(TCG_REG_TMP1, 0, addr >> 16);
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i2 = ORI | SAI(TCG_REG_TMP1, TCG_REG_TMP1, addr);
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}
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/* This does not exercise the range of the branch, but we do
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still need to be able to load the new value of TCG_REG_TB.
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But this does still happen quite often. */
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if (tb_diff == (int16_t)tb_diff) {
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i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
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i2 = B | (br_diff & 0x3fffffc);
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} else {
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intptr_t lo = (int16_t)tb_diff;
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intptr_t hi = (int32_t)(tb_diff - lo);
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assert(tb_diff == hi + lo);
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i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
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i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
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}
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#ifdef HOST_WORDS_BIGENDIAN
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pair = (uint64_t)i1 << 32 | i2;
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pair = (uint64_t)i1 << 32 | i2;
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#else
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pair = (uint64_t)i2 << 32 | i1;
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pair = (uint64_t)i2 << 32 | i1;
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#endif
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atomic_set((uint64_t *)jmp_addr, pair);
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flush_icache_range(jmp_addr, jmp_addr + 8);
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atomic_set((uint64_t *)jmp_addr, pair);
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flush_icache_range(jmp_addr, jmp_addr + 8);
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} else {
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intptr_t diff = addr - jmp_addr;
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tcg_debug_assert(in_range_b(diff));
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atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
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flush_icache_range(jmp_addr, jmp_addr + 4);
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}
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}
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#else
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void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
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uintptr_t addr)
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{
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intptr_t diff = addr - jmp_addr;
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tcg_debug_assert(in_range_b(diff));
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atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc));
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flush_icache_range(jmp_addr, jmp_addr + 4);
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}
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#endif
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static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
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{
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@ -1897,44 +1888,20 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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#ifndef CONFIG_SOFTMMU
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if (guest_base) {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
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tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
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tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
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}
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#endif
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
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if (USE_REG_RA) {
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#ifdef _CALL_AIX
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/* Make the caller load the value as the TOC into R2. */
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tb_ret_addr = s->code_ptr + 2;
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desc[1] = tb_ret_addr;
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_RA, TCG_REG_R2);
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tcg_out32(s, BCCTR | BO_ALWAYS);
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#elif defined(_CALL_ELF) && _CALL_ELF == 2
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/* Compute from the incoming R12 value. */
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tb_ret_addr = s->code_ptr + 2;
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tcg_out32(s, ADDI | TAI(TCG_REG_RA, TCG_REG_R12,
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tcg_ptr_byte_diff(tb_ret_addr, s->code_buf)));
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tcg_out32(s, BCCTR | BO_ALWAYS);
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#else
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/* Reserve max 5 insns for the constant load. */
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tb_ret_addr = s->code_ptr + 6;
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)tb_ret_addr);
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tcg_out32(s, BCCTR | BO_ALWAYS);
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while (s->code_ptr < tb_ret_addr) {
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tcg_out32(s, NOP);
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}
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#endif
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} else {
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tcg_out32(s, BCCTR | BO_ALWAYS);
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tb_ret_addr = s->code_ptr;
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if (USE_REG_TB) {
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
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}
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tcg_out32(s, BCCTR | BO_ALWAYS);
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/* Epilogue */
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tcg_debug_assert(tb_ret_addr == s->code_ptr);
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s->code_gen_epilogue = tb_ret_addr;
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s->code_gen_epilogue = tb_ret_addr = s->code_ptr;
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
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for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
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@ -1954,44 +1921,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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switch (opc) {
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case INDEX_op_exit_tb:
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if (USE_REG_RA) {
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ptrdiff_t disp = tcg_pcrel_diff(s, tb_ret_addr);
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/* Use a direct branch if we can, otherwise use the value in RA.
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Note that the direct branch is always backward, thus we need
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to account for the possibility of 5 insns from the movi. */
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if (!in_range_b(disp - 20)) {
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tcg_out32(s, MTSPR | RS(TCG_REG_RA) | CTR);
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
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tcg_out32(s, BCCTR | BO_ALWAYS);
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break;
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}
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}
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
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tcg_out_b(s, 0, tb_ret_addr);
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break;
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case INDEX_op_goto_tb:
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tcg_debug_assert(s->tb_jmp_insn_offset);
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/* Direct jump. */
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#ifdef __powerpc64__
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/* Ensure the next insns are 8-byte aligned. */
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if ((uintptr_t)s->code_ptr & 7) {
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tcg_out32(s, NOP);
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if (s->tb_jmp_insn_offset) {
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/* Direct jump. */
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if (TCG_TARGET_REG_BITS == 64) {
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/* Ensure the next insns are 8-byte aligned. */
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if ((uintptr_t)s->code_ptr & 7) {
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tcg_out32(s, NOP);
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}
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s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
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tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0));
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tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0));
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} else {
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s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
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tcg_out32(s, B);
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s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
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break;
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}
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} else {
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/* Indirect jump. */
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tcg_debug_assert(s->tb_jmp_insn_offset == NULL);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0,
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(intptr_t)(s->tb_jmp_insn_offset + args[0]));
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}
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s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
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/* To be replaced by either a branch+nop or a load into TMP1. */
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s->code_ptr += 2;
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tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR);
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tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR);
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tcg_out32(s, BCCTR | BO_ALWAYS);
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#else
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/* To be replaced by a branch. */
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s->code_ptr++;
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#endif
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s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
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s->tb_jmp_reset_offset[args[0]] = c = tcg_current_code_size(s);
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if (USE_REG_TB) {
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/* For the unlinked case, need to reset TCG_REG_TB. */
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c = -c;
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assert(c == (int16_t)c);
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tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c));
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}
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break;
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case INDEX_op_goto_ptr:
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tcg_out32(s, MTSPR | RS(args[0]) | CTR);
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, 0);
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if (USE_REG_TB) {
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]);
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}
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tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0));
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tcg_out32(s, BCCTR | BO_ALWAYS);
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break;
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case INDEX_op_br:
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@ -2761,8 +2732,8 @@ static void tcg_target_init(TCGContext *s)
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
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#endif
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
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if (USE_REG_RA) {
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr */
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if (USE_REG_TB) {
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
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}
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}
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