target/mips: Add emulation of MXU instructions for 32-bit load/store
Add support for emulating: - S32LDDV and S32LDDVR - S32STD and S32STDR - S32STDV and S32STDVR MXU instructions. Add support for emulating MXU instructions with address register post-modify counterparts: - S32LDI and S32LDIR - S32LDIV and S32LDIVR - S32SDI and S32SDIR - S32SDIV and S32SDIVR Refactor support for emulating the S32LDD and S32LDDR instructions. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-2-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Siarhei Volkau
Philippe Mathieu-Daudé
parent
99eff13120
commit
59db94656d
@ -237,11 +237,11 @@
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* ├─ 001100 ─ OPC_MXU_D16MADL
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* ├─ 001101 ─ OPC_MXU_S16MAD
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* ├─ 001110 ─ OPC_MXU_Q16ADD
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* ├─ 001111 ─ OPC_MXU_D16MACE 23
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* ├─ 001111 ─ OPC_MXU_D16MACE 20 (13..10 don't care)
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* │ ┌─ 0 ─ OPC_MXU_S32LDD
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* ├─ 010000 ─ OPC_MXU__POOL04 ─┴─ 1 ─ OPC_MXU_S32LDDR
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* │
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* │ 23
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* │ 20 (13..10 don't care)
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* ├─ 010001 ─ OPC_MXU__POOL05 ─┬─ 0 ─ OPC_MXU_S32STD
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* │ └─ 1 ─ OPC_MXU_S32STDR
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* │
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@ -253,11 +253,11 @@
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* ├─ 010011 ─ OPC_MXU__POOL07 ─┬─ 0000 ─ OPC_MXU_S32STDV
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* │ └─ 0001 ─ OPC_MXU_S32STDVR
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* │
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* │ 23
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* │ 20 (13..10 don't care)
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* ├─ 010100 ─ OPC_MXU__POOL08 ─┬─ 0 ─ OPC_MXU_S32LDI
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* │ └─ 1 ─ OPC_MXU_S32LDIR
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* │
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* │ 23
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* │ 20 (13..10 don't care)
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* ├─ 010101 ─ OPC_MXU__POOL09 ─┬─ 0 ─ OPC_MXU_S32SDI
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* │ └─ 1 ─ OPC_MXU_S32SDIR
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* │
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@ -357,6 +357,13 @@ enum {
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OPC_MXU_D16MUL = 0x08,
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OPC_MXU_D16MAC = 0x0A,
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OPC_MXU__POOL04 = 0x10,
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OPC_MXU__POOL05 = 0x11,
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OPC_MXU__POOL06 = 0x12,
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OPC_MXU__POOL07 = 0x13,
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OPC_MXU__POOL08 = 0x14,
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OPC_MXU__POOL09 = 0x15,
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OPC_MXU__POOL10 = 0x16,
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OPC_MXU__POOL11 = 0x17,
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OPC_MXU_S8LDD = 0x22,
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OPC_MXU__POOL16 = 0x27,
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OPC_MXU_S32M2I = 0x2E,
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@ -378,11 +385,11 @@ enum {
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};
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/*
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* MXU pool 04
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* MXU pool 04 05 06 07 08 09 10 11
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*/
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enum {
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OPC_MXU_S32LDD = 0x00,
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OPC_MXU_S32LDDR = 0x01,
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OPC_MXU_S32LDST = 0x00,
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OPC_MXU_S32LDSTR = 0x01,
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};
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/*
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@ -806,35 +813,147 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
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/*
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* S32LDD XRa, Rb, S12 - Load a word from memory to XRF
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* S32LDDR XRa, Rb, S12 - Load a word from memory to XRF, reversed byte seq.
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* S32LDDR XRa, Rb, S12 - Load a word from memory to XRF
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* in reversed byte seq.
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* S32LDI XRa, Rb, S12 - Load a word from memory to XRF,
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* post modify base address GPR.
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* S32LDIR XRa, Rb, S12 - Load a word from memory to XRF,
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* post modify base address GPR and load in reversed byte seq.
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*/
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static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
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static void gen_mxu_s32ldxx(DisasContext *ctx, bool reversed, bool postinc)
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{
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TCGv t0, t1;
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uint32_t XRa, Rb, s12, sel;
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uint32_t XRa, Rb, s12;
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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XRa = extract32(ctx->opcode, 6, 4);
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s12 = extract32(ctx->opcode, 10, 10);
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sel = extract32(ctx->opcode, 20, 1);
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s12 = sextract32(ctx->opcode, 10, 10);
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Rb = extract32(ctx->opcode, 21, 5);
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gen_load_gpr(t0, Rb);
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tcg_gen_movi_tl(t1, s12 * 4);
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tcg_gen_add_tl(t0, t0, t1);
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tcg_gen_movi_tl(t1, s12);
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tcg_gen_shli_tl(t1, t1, 2);
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if (s12 & 0x200) {
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tcg_gen_ori_tl(t1, t1, 0xFFFFF000);
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}
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tcg_gen_add_tl(t1, t0, t1);
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tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, (MO_TESL ^ (sel * MO_BSWAP)) |
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ctx->default_tcg_memop_mask);
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tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
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(MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
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ctx->default_tcg_memop_mask);
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gen_store_mxu_gpr(t1, XRa);
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if (postinc) {
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gen_store_gpr(t0, Rb);
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}
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}
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/*
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* S32STD XRa, Rb, S12 - Store a word from XRF to memory
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* S32STDR XRa, Rb, S12 - Store a word from XRF to memory
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* in reversed byte seq.
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* S32SDI XRa, Rb, S12 - Store a word from XRF to memory,
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* post modify base address GPR.
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* S32SDIR XRa, Rb, S12 - Store a word from XRF to memory,
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* post modify base address GPR and store in reversed byte seq.
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*/
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static void gen_mxu_s32stxx(DisasContext *ctx, bool reversed, bool postinc)
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{
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TCGv t0, t1;
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uint32_t XRa, Rb, s12;
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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XRa = extract32(ctx->opcode, 6, 4);
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s12 = sextract32(ctx->opcode, 10, 10);
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Rb = extract32(ctx->opcode, 21, 5);
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gen_load_gpr(t0, Rb);
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tcg_gen_movi_tl(t1, s12 * 4);
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tcg_gen_add_tl(t0, t0, t1);
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gen_load_mxu_gpr(t1, XRa);
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
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(MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
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ctx->default_tcg_memop_mask);
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if (postinc) {
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gen_store_gpr(t0, Rb);
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}
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}
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/*
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* S32LDDV XRa, Rb, Rc, STRD2 - Load a word from memory to XRF
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* S32LDDVR XRa, Rb, Rc, STRD2 - Load a word from memory to XRF
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* in reversed byte seq.
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* S32LDIV XRa, Rb, Rc, STRD2 - Load a word from memory to XRF,
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* post modify base address GPR.
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* S32LDIVR XRa, Rb, Rc, STRD2 - Load a word from memory to XRF,
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* post modify base address GPR and load in reversed byte seq.
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*/
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static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,
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bool postinc, uint32_t strd2)
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{
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TCGv t0, t1;
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uint32_t XRa, Rb, Rc;
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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XRa = extract32(ctx->opcode, 6, 4);
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Rc = extract32(ctx->opcode, 16, 5);
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Rb = extract32(ctx->opcode, 21, 5);
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gen_load_gpr(t0, Rb);
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gen_load_gpr(t1, Rc);
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tcg_gen_shli_tl(t1, t1, strd2);
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tcg_gen_add_tl(t0, t0, t1);
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tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
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(MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
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ctx->default_tcg_memop_mask);
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gen_store_mxu_gpr(t1, XRa);
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if (postinc) {
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gen_store_gpr(t0, Rb);
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}
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}
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/*
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* S32STDV XRa, Rb, Rc, STRD2 - Load a word from memory to XRF
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* S32STDVR XRa, Rb, Rc, STRD2 - Load a word from memory to XRF
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* in reversed byte seq.
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* S32SDIV XRa, Rb, Rc, STRD2 - Load a word from memory to XRF,
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* post modify base address GPR.
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* S32SDIVR XRa, Rb, Rc, STRD2 - Load a word from memory to XRF,
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* post modify base address GPR and store in reversed byte seq.
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*/
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static void gen_mxu_s32stxvx(DisasContext *ctx, bool reversed,
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bool postinc, uint32_t strd2)
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{
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TCGv t0, t1;
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uint32_t XRa, Rb, Rc;
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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XRa = extract32(ctx->opcode, 6, 4);
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Rc = extract32(ctx->opcode, 16, 5);
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Rb = extract32(ctx->opcode, 21, 5);
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gen_load_gpr(t0, Rb);
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gen_load_gpr(t1, Rc);
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tcg_gen_shli_tl(t1, t1, strd2);
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tcg_gen_add_tl(t0, t0, t1);
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gen_load_mxu_gpr(t1, XRa);
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
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(MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
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ctx->default_tcg_memop_mask);
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if (postinc) {
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gen_store_gpr(t0, Rb);
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}
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}
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/*
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* MXU instruction category: logic
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@ -1440,13 +1559,129 @@ static void decode_opc_mxu__pool00(DisasContext *ctx)
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static void decode_opc_mxu__pool04(DisasContext *ctx)
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{
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uint32_t opcode = extract32(ctx->opcode, 20, 1);
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uint32_t reversed = extract32(ctx->opcode, 20, 1);
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uint32_t opcode = extract32(ctx->opcode, 10, 4);
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/* Don't care about opcode bits as their meaning is unknown yet */
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switch (opcode) {
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default:
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gen_mxu_s32ldxx(ctx, reversed, false);
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break;
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}
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}
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static void decode_opc_mxu__pool05(DisasContext *ctx)
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{
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uint32_t reversed = extract32(ctx->opcode, 20, 1);
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uint32_t opcode = extract32(ctx->opcode, 10, 4);
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/* Don't care about opcode bits as their meaning is unknown yet */
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switch (opcode) {
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default:
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gen_mxu_s32stxx(ctx, reversed, false);
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break;
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}
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}
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static void decode_opc_mxu__pool06(DisasContext *ctx)
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{
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uint32_t opcode = extract32(ctx->opcode, 10, 4);
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uint32_t strd2 = extract32(ctx->opcode, 14, 2);
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switch (opcode) {
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case OPC_MXU_S32LDD:
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case OPC_MXU_S32LDDR:
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gen_mxu_s32ldd_s32lddr(ctx);
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case OPC_MXU_S32LDST:
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case OPC_MXU_S32LDSTR:
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if (strd2 <= 2) {
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gen_mxu_s32ldxvx(ctx, opcode, false, strd2);
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break;
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}
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/* fallthrough */
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default:
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MIPS_INVAL("decode_opc_mxu");
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gen_reserved_instruction(ctx);
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break;
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}
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}
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static void decode_opc_mxu__pool07(DisasContext *ctx)
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{
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uint32_t opcode = extract32(ctx->opcode, 10, 4);
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uint32_t strd2 = extract32(ctx->opcode, 14, 2);
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switch (opcode) {
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case OPC_MXU_S32LDST:
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case OPC_MXU_S32LDSTR:
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if (strd2 <= 2) {
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gen_mxu_s32stxvx(ctx, opcode, false, strd2);
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break;
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}
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/* fallthrough */
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default:
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MIPS_INVAL("decode_opc_mxu");
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gen_reserved_instruction(ctx);
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break;
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}
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}
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static void decode_opc_mxu__pool08(DisasContext *ctx)
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{
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uint32_t reversed = extract32(ctx->opcode, 20, 1);
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uint32_t opcode = extract32(ctx->opcode, 10, 4);
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/* Don't care about opcode bits as their meaning is unknown yet */
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switch (opcode) {
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default:
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gen_mxu_s32ldxx(ctx, reversed, true);
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break;
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}
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}
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static void decode_opc_mxu__pool09(DisasContext *ctx)
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{
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uint32_t reversed = extract32(ctx->opcode, 20, 1);
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uint32_t opcode = extract32(ctx->opcode, 10, 4);
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/* Don't care about opcode bits as their meaning is unknown yet */
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switch (opcode) {
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default:
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gen_mxu_s32stxx(ctx, reversed, true);
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break;
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}
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}
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static void decode_opc_mxu__pool10(DisasContext *ctx)
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{
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uint32_t opcode = extract32(ctx->opcode, 10, 4);
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uint32_t strd2 = extract32(ctx->opcode, 14, 2);
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switch (opcode) {
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case OPC_MXU_S32LDST:
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case OPC_MXU_S32LDSTR:
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if (strd2 <= 2) {
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gen_mxu_s32ldxvx(ctx, opcode, true, strd2);
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break;
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}
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/* fallthrough */
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default:
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MIPS_INVAL("decode_opc_mxu");
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gen_reserved_instruction(ctx);
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break;
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}
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}
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static void decode_opc_mxu__pool11(DisasContext *ctx)
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{
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uint32_t opcode = extract32(ctx->opcode, 10, 4);
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uint32_t strd2 = extract32(ctx->opcode, 14, 2);
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switch (opcode) {
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case OPC_MXU_S32LDST:
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case OPC_MXU_S32LDSTR:
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if (strd2 <= 2) {
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gen_mxu_s32stxvx(ctx, opcode, true, strd2);
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break;
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}
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/* fallthrough */
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default:
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MIPS_INVAL("decode_opc_mxu");
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gen_reserved_instruction(ctx);
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@ -1532,6 +1767,27 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
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case OPC_MXU__POOL04:
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decode_opc_mxu__pool04(ctx);
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break;
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case OPC_MXU__POOL05:
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decode_opc_mxu__pool05(ctx);
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break;
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case OPC_MXU__POOL06:
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decode_opc_mxu__pool06(ctx);
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break;
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case OPC_MXU__POOL07:
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decode_opc_mxu__pool07(ctx);
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break;
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case OPC_MXU__POOL08:
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decode_opc_mxu__pool08(ctx);
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break;
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case OPC_MXU__POOL09:
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decode_opc_mxu__pool09(ctx);
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break;
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case OPC_MXU__POOL10:
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decode_opc_mxu__pool10(ctx);
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break;
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case OPC_MXU__POOL11:
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decode_opc_mxu__pool11(ctx);
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break;
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case OPC_MXU_S8LDD:
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gen_mxu_s8ldd(ctx);
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break;
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