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hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask() 

hw_error() calls exit(). This a bit overkill when we can log
the accesses as unimplemented or guest error.

When fuzzing the devices, we don't want the whole process to
exit. Replace some hw_error() calls by qemu_log_mask().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200518140309.5220-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-05-18 16:03:07 +02:00 committed by Peter Maydell
parent 9904625f1b
commit 5a0001ec7e
3 changed files with 18 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
hw/arm/pxa2xx_gpio.c
View File

@ -9,7 +9,6 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "cpu.h" #include "cpu.h"
#include "hw/hw.h"
#include "hw/irq.h" #include "hw/irq.h"
#include "hw/qdev-properties.h" #include "hw/qdev-properties.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
@ -199,7 +198,8 @@ static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
return s->status[bank]; return s->status[bank];
default: default:
hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
__func__, offset);
} }
return 0; return 0;
@ -252,7 +252,8 @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
break; break;
default: default:
hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
__func__, offset);
} }
} }

8
hw/display/pxa2xx_lcd.c
View File

@ -11,7 +11,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "hw/hw.h" #include "qemu/log.h"
#include "hw/irq.h" #include "hw/irq.h"
#include "migration/vmstate.h" #include "migration/vmstate.h"
#include "ui/console.h" #include "ui/console.h"
@ -407,7 +407,8 @@ static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
default: default:
fail: fail:
hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
__func__, offset);
} }
return 0; return 0;
@ -562,7 +563,8 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
default: default:
fail: fail:
hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
__func__, offset);
} }
} }

14
hw/dma/pxa2xx_dma.c
View File

@ -9,6 +9,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/irq.h" #include "hw/irq.h"
#include "hw/qdev-properties.h" #include "hw/qdev-properties.h"
@ -268,7 +269,8 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
unsigned int channel; unsigned int channel;
if (size != 4) { if (size != 4) {
hw_error("%s: Bad access width\n", __func__); qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
__func__, size);
return 5; return 5;
} }
@ -315,8 +317,8 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
return s->chan[channel].cmd; return s->chan[channel].cmd;
} }
} }
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); __func__, offset);
return 7; return 7;
} }
@ -327,7 +329,8 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
unsigned int channel; unsigned int channel;
if (size != 4) { if (size != 4) {
hw_error("%s: Bad access width\n", __func__); qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
__func__, size);
return; return;
} }
@ -420,7 +423,8 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
break; break;
} }
fail: fail:
hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset); qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
__func__, offset);
} }
} }