qemu: clean up target page usage in msix
Since cpu_register_phys_memory does not require size to be a multiple of
target page size, simply make msix page size 0x1000. Do this in msix,
reverting part of 5e520a7d50, as we no
longer have to pass target page around.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Michael S. Tsirkin
Anthony Liguori
parent
8f2498f9f6
commit
5a1fc5e852
49
hw/msix.c
49
hw/msix.c
@ -38,6 +38,13 @@
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#define MSIX_VECTOR_CTRL 12
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#define MSIX_ENTRY_SIZE 16
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#define MSIX_VECTOR_MASK 0x1
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/* How much space does an MSIX table need. */
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/* The spec requires giving the table structure
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* a 4K aligned region all by itself. */
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#define MSIX_PAGE_SIZE 0x1000
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/* Reserve second half of the page for pending bits */
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#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
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#define MSIX_MAX_ENTRIES 32
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@ -53,12 +60,6 @@
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/* Flag for interrupt controller to declare MSI-X support */
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int msix_supported;
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/* Reserve second half of the page for pending bits */
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static int msix_page_pending(PCIDevice *d)
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{
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return (d->msix_page_size / 2);
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}
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/* Add MSI-X capability to the config space for the device. */
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/* Given a bar and its size, add MSI-X table on top of it
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* and fill MSI-X capability in the config space.
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@ -78,12 +79,13 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
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/* Add space for MSI-X structures */
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if (!bar_size) {
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new_size = pdev->msix_page_size;
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} else if (bar_size < pdev->msix_page_size) {
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bar_size = pdev->msix_page_size;
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new_size = pdev->msix_page_size * 2;
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} else
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new_size = MSIX_PAGE_SIZE;
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} else if (bar_size < MSIX_PAGE_SIZE) {
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bar_size = MSIX_PAGE_SIZE;
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new_size = MSIX_PAGE_SIZE * 2;
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} else {
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new_size = bar_size * 2;
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}
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pdev->msix_bar_size = new_size;
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config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
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@ -95,8 +97,8 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
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/* Table on top of BAR */
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pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr);
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/* Pending bits on top of that */
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pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + msix_page_pending(pdev))
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| bar_nr);
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pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
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bar_nr);
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pdev->msix_cap = config_offset;
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/* Make flags bit writeable. */
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pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
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@ -126,7 +128,7 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
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static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
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{
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PCIDevice *dev = opaque;
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unsigned int offset = addr & (dev->msix_page_size - 1);
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unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
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void *page = dev->msix_table_page;
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uint32_t val = 0;
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@ -148,7 +150,7 @@ static uint8_t msix_pending_mask(int vector)
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static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
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{
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return dev->msix_table_page + msix_page_pending(dev) + vector / 8;
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return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
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}
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static int msix_is_pending(PCIDevice *dev, int vector)
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@ -176,7 +178,7 @@ static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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PCIDevice *dev = opaque;
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unsigned int offset = addr & (dev->msix_page_size - 1);
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unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
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int vector = offset / MSIX_ENTRY_SIZE;
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memcpy(dev->msix_table_page + offset, &val, 4);
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if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
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@ -205,7 +207,7 @@ void msix_mmio_map(PCIDevice *d, int region_num,
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{
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uint8_t *config = d->config + d->msix_cap;
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uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
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uint32_t offset = table & ~(d->msix_page_size - 1);
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uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
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/* TODO: for assigned devices, we'll want to make it possible to map
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* pending bits separately in case they are in a separate bar. */
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int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
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@ -221,7 +223,7 @@ void msix_mmio_map(PCIDevice *d, int region_num,
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/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
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* modified, it should be retrieved with msix_bar_size. */
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int msix_init(struct PCIDevice *dev, unsigned short nentries,
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unsigned bar_nr, unsigned bar_size, target_phys_addr_t page_size)
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unsigned bar_nr, unsigned bar_size)
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{
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int ret;
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/* Nothing to do if MSI is not supported by interrupt controller */
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@ -234,8 +236,7 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries,
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dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
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sizeof *dev->msix_entry_used);
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dev->msix_page_size = page_size;
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dev->msix_table_page = qemu_mallocz(dev->msix_page_size);
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dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
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dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
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msix_mmio_write, dev);
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@ -290,8 +291,7 @@ void msix_save(PCIDevice *dev, QEMUFile *f)
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}
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qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
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qemu_put_buffer(f, dev->msix_table_page + msix_page_pending(dev),
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(n + 7) / 8);
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qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
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}
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/* Should be called after restoring the config space. */
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@ -305,8 +305,7 @@ void msix_load(PCIDevice *dev, QEMUFile *f)
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msix_free_irq_entries(dev);
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qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
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qemu_get_buffer(f, dev->msix_table_page + msix_page_pending(dev),
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(n + 7) / 8);
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qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
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}
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/* Does device support MSI-X? */
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@ -356,7 +355,7 @@ void msix_reset(PCIDevice *dev)
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return;
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msix_free_irq_entries(dev);
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dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK;
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memset(dev->msix_table_page, 0, dev->msix_page_size);
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memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
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}
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/* PCI spec suggests that devices make it possible for software to configure
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@ -3,9 +3,8 @@
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#include "qemu-common.h"
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int msix_init(struct PCIDevice *dev, unsigned short nentries,
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unsigned bar_nr, unsigned bar_size,
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target_phys_addr_t page_size);
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int msix_init(PCIDevice *pdev, unsigned short nentries,
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unsigned bar_nr, unsigned bar_size);
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void msix_write_config(PCIDevice *pci_dev, uint32_t address,
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uint32_t val, int len);
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6
hw/pci.h
6
hw/pci.h
@ -213,12 +213,6 @@ struct PCIDevice {
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uint32_t msix_bar_size;
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/* Version id needed for VMState */
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int32_t version_id;
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/* How much space does an MSIX table need. */
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/* The spec requires giving the table structure
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* a 4K aligned region all by itself. Align it to
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* target pages so that drivers can do passthrough
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* on the rest of the region. */
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target_phys_addr_t msix_page_size;
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};
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PCIDevice *pci_register_device(PCIBus *bus, const char *name,
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@ -411,8 +411,7 @@ static void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev,
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config[0x3d] = 1;
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if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors, 1, 0,
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TARGET_PAGE_SIZE)) {
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if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors, 1, 0)) {
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pci_register_bar(&proxy->pci_dev, 1,
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msix_bar_size(&proxy->pci_dev),
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PCI_ADDRESS_SPACE_MEM,
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