hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device
Connect the Cadence GEM ethernet device. This also requires us to expose the plic interrupt lines. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Clark <mjc@sifive.com>
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@ -3,3 +3,5 @@
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CONFIG_SERIAL=y
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CONFIG_SERIAL=y
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CONFIG_VIRTIO_MMIO=y
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CONFIG_VIRTIO_MMIO=y
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include virtio.mak
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include virtio.mak
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CONFIG_CADENCE=y
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@ -3,3 +3,5 @@
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CONFIG_SERIAL=y
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CONFIG_SERIAL=y
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CONFIG_VIRTIO_MMIO=y
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CONFIG_VIRTIO_MMIO=y
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include virtio.mak
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include virtio.mak
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CONFIG_CADENCE=y
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@ -60,8 +60,11 @@ static const struct MemmapEntry {
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[SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
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[SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
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[SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
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[SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
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[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
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[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
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[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
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};
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};
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#define GEM_REVISION 0x10070109
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static uint64_t load_kernel(const char *kernel_filename)
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static uint64_t load_kernel(const char *kernel_filename)
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{
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{
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uint64_t kernel_entry, kernel_high;
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uint64_t kernel_entry, kernel_high;
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@ -194,6 +197,27 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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g_free(cells);
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g_free(cells);
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g_free(nodename);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/ethernet@%lx",
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(long)memmap[SIFIVE_U_GEM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_GEM].base,
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0x0, memmap[SIFIVE_U_GEM].size);
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qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
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qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
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qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
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qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
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qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
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(long)memmap[SIFIVE_U_GEM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/uart@%lx",
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nodename = g_strdup_printf("/soc/uart@%lx",
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(long)memmap[SIFIVE_U_UART0].base);
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(long)memmap[SIFIVE_U_UART0].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_add_subnode(fdt, nodename);
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@ -286,6 +310,9 @@ static void riscv_sifive_u_soc_init(Object *obj)
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&error_abort);
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&error_abort);
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object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
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object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
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&error_abort);
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&error_abort);
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object_initialize(&s->gem, sizeof(s->gem), TYPE_CADENCE_GEM);
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qdev_set_parent_bus(DEVICE(&s->gem), sysbus_get_default());
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}
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}
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static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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@ -294,6 +321,10 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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const struct MemmapEntry *memmap = sifive_u_memmap;
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const struct MemmapEntry *memmap = sifive_u_memmap;
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
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int i;
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Error *err = NULL;
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NICInfo *nd = &nd_table[0];
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object_property_set_bool(OBJECT(&s->cpus), true, "realized",
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object_property_set_bool(OBJECT(&s->cpus), true, "realized",
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&error_abort);
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&error_abort);
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@ -324,6 +355,25 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
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sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
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memmap[SIFIVE_U_CLINT].size, smp_cpus,
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memmap[SIFIVE_U_CLINT].size, smp_cpus,
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SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
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SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
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for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
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plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
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}
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if (nd->used) {
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qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
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qdev_set_nic_properties(DEVICE(&s->gem), nd);
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}
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object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
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&error_abort);
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object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
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plic_gpios[SIFIVE_U_GEM_IRQ]);
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}
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}
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static void riscv_sifive_u_machine_init(MachineClass *mc)
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static void riscv_sifive_u_machine_init(MachineClass *mc)
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@ -19,6 +19,8 @@
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#ifndef HW_SIFIVE_U_H
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#ifndef HW_SIFIVE_U_H
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#define HW_SIFIVE_U_H
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#define HW_SIFIVE_U_H
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#include "hw/net/cadence_gem.h"
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#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
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#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
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#define RISCV_U_SOC(obj) \
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#define RISCV_U_SOC(obj) \
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OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
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OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
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@ -30,6 +32,7 @@ typedef struct SiFiveUSoCState {
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/*< public >*/
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/*< public >*/
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RISCVHartArrayState cpus;
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RISCVHartArrayState cpus;
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DeviceState *plic;
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DeviceState *plic;
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CadenceGEMState gem;
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} SiFiveUSoCState;
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} SiFiveUSoCState;
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typedef struct SiFiveUState {
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typedef struct SiFiveUState {
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@ -49,12 +52,14 @@ enum {
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SIFIVE_U_PLIC,
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SIFIVE_U_PLIC,
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SIFIVE_U_UART0,
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SIFIVE_U_UART0,
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SIFIVE_U_UART1,
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SIFIVE_U_UART1,
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SIFIVE_U_DRAM
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SIFIVE_U_DRAM,
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SIFIVE_U_GEM
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};
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};
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enum {
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enum {
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SIFIVE_U_UART0_IRQ = 3,
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SIFIVE_U_UART0_IRQ = 3,
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SIFIVE_U_UART1_IRQ = 4
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SIFIVE_U_UART1_IRQ = 4,
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SIFIVE_U_GEM_IRQ = 0x35
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};
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};
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enum {
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enum {
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