From 5aa7f68a2df9604dbd7f95e9ecece6d553e46e32 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 28 Apr 2021 16:16:53 +0200 Subject: [PATCH] hw/sparc64: Fix code style for checkpatch.pl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: KONRAD Frederic Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson Message-Id: <20210428141655.387430-4-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland --- hw/sparc64/sparc64.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index cc0b9bd30d..fd29a79edc 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -48,14 +48,18 @@ void cpu_check_irqs(CPUSPARCState *env) return; } cs = env_cpu(env); - /* check if TM or SM in SOFTINT are set - setting these also causes interrupt 14 */ + /* + * check if TM or SM in SOFTINT are set + * setting these also causes interrupt 14 + */ if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { pil |= 1 << 14; } - /* The bit corresponding to psrpil is (1<< psrpil), the next bit - is (2 << psrpil). */ + /* + * The bit corresponding to psrpil is (1<< psrpil), + * the next bit is (2 << psrpil). + */ if (pil < (2 << env->psrpil)) { if (cs->interrupt_request & CPU_INTERRUPT_HARD) { trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);