target/riscv: rvv: Add mask agnostic for vector floating-point instructions
Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-7@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Yueh-Ting (eop) Chen
Alistair Francis
parent
72e17a9f86
commit
5b448f44c9
@ -2361,6 +2361,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = \
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FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs1), \
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vreg_ofs(s, a->rs2), cpu_env, \
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@ -2446,6 +2447,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VTA_ALL_1S, \
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s->cfg_vta_all_1s); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
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fns[s->sew - 1], s); \
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} \
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@ -2485,6 +2487,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs1), \
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vreg_ofs(s, a->rs2), cpu_env, \
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@ -2525,6 +2528,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
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fns[s->sew - 1], s); \
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} \
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@ -2562,6 +2566,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs1), \
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vreg_ofs(s, a->rs2), cpu_env, \
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@ -2602,6 +2607,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
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fns[s->sew - 1], s); \
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} \
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@ -2686,6 +2692,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
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data = FIELD_DP32(data, VDATA, VM, a->vm);
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
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data = FIELD_DP32(data, VDATA, VTA, s->vta);
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data = FIELD_DP32(data, VDATA, VMA, s->vma);
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tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
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vreg_ofs(s, a->rs2), cpu_env,
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s->cfg_ptr->vlen / 8,
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@ -2790,6 +2797,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
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TCGv_i32 desc;
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uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
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data = FIELD_DP32(data, VDATA, VTA, s->vta);
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data = FIELD_DP32(data, VDATA, VMA, s->vma);
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static gen_helper_vmv_vx * const fns[3] = {
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gen_helper_vmv_v_x_h,
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gen_helper_vmv_v_x_w,
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@ -2891,6 +2899,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs2), cpu_env, \
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s->cfg_ptr->vlen / 8, \
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@ -2944,6 +2953,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs2), cpu_env, \
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s->cfg_ptr->vlen / 8, \
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@ -3012,6 +3022,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs2), cpu_env, \
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s->cfg_ptr->vlen / 8, \
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@ -3067,6 +3078,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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data = FIELD_DP32(data, VDATA, VTA, s->vta); \
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data = FIELD_DP32(data, VDATA, VMA, s->vma); \
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tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs2), cpu_env, \
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s->cfg_ptr->vlen / 8, \
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@ -3051,10 +3051,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
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uint32_t total_elems = \
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vext_get_total_elems(env, desc, ESZ); \
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uint32_t vta = vext_vta(desc); \
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uint32_t vma = vext_vma(desc); \
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uint32_t i; \
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\
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for (i = env->vstart; i < vl; i++) { \
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if (!vm && !vext_elem_mask(v0, i)) { \
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/* set masked-off elements to 1s */ \
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vext_set_elems_1s(vd, vma, i * ESZ, \
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(i + 1) * ESZ); \
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continue; \
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} \
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do_##NAME(vd, vs1, vs2, i, env); \
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@ -3090,10 +3094,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
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uint32_t total_elems = \
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vext_get_total_elems(env, desc, ESZ); \
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uint32_t vta = vext_vta(desc); \
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uint32_t vma = vext_vma(desc); \
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uint32_t i; \
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\
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for (i = env->vstart; i < vl; i++) { \
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if (!vm && !vext_elem_mask(v0, i)) { \
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/* set masked-off elements to 1s */ \
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vext_set_elems_1s(vd, vma, i * ESZ, \
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(i + 1) * ESZ); \
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continue; \
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} \
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do_##NAME(vd, s1, vs2, i, env); \
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@ -3665,6 +3673,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
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uint32_t total_elems = \
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vext_get_total_elems(env, desc, ESZ); \
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uint32_t vta = vext_vta(desc); \
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uint32_t vma = vext_vma(desc); \
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uint32_t i; \
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\
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if (vl == 0) { \
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@ -3672,6 +3681,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
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} \
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for (i = env->vstart; i < vl; i++) { \
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if (!vm && !vext_elem_mask(v0, i)) { \
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/* set masked-off elements to 1s */ \
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vext_set_elems_1s(vd, vma, i * ESZ, \
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(i + 1) * ESZ); \
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continue; \
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} \
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do_##NAME(vd, vs2, i, env); \
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@ -4182,12 +4194,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
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uint32_t vl = env->vl; \
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uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
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uint32_t vta_all_1s = vext_vta_all_1s(desc); \
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uint32_t vma = vext_vma(desc); \
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uint32_t i; \
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\
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for (i = env->vstart; i < vl; i++) { \
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ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
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ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
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if (!vm && !vext_elem_mask(v0, i)) { \
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/* set masked-off elements to 1s */ \
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if (vma) { \
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vext_set_elem_mask(vd, i, 1); \
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} \
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continue; \
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} \
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vext_set_elem_mask(vd, i, \
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@ -4215,11 +4232,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
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uint32_t vl = env->vl; \
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uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
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uint32_t vta_all_1s = vext_vta_all_1s(desc); \
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uint32_t vma = vext_vma(desc); \
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uint32_t i; \
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\
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for (i = env->vstart; i < vl; i++) { \
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ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
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if (!vm && !vext_elem_mask(v0, i)) { \
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/* set masked-off elements to 1s */ \
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if (vma) { \
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vext_set_elem_mask(vd, i, 1); \
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} \
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continue; \
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} \
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vext_set_elem_mask(vd, i, \
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@ -4342,10 +4364,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
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uint32_t total_elems = \
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vext_get_total_elems(env, desc, ESZ); \
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uint32_t vta = vext_vta(desc); \
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uint32_t vma = vext_vma(desc); \
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uint32_t i; \
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\
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for (i = env->vstart; i < vl; i++) { \
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if (!vm && !vext_elem_mask(v0, i)) { \
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/* set masked-off elements to 1s */ \
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vext_set_elems_1s(vd, vma, i * ESZ, \
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(i + 1) * ESZ); \
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continue; \
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} \
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do_##NAME(vd, vs2, i); \
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