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hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN

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The CCR is a register most of whose bits are banked between security
states but where BFHFNMIGN is not, and we keep it in the non-secure
entry of the v7m.ccr[] array.  The logic which tries to handle this
bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS
is zero" requirement; correct the omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201210201433.26262-2-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-12-10 20:14:30 +00:00
parent cc97b0019b
commit 5b7d63706e
1 changed files with 15 additions and 0 deletions
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15
hw/intc/armv7m_nvic.c
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@ -1106,6 +1106,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
*/
val = cpu->env.v7m.ccr[attrs.secure];
val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
/* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */
if (!attrs.secure) {
if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
val &= ~R_V7M_CCR_BFHFNMIGN_MASK;
}
}
return val;
case 0xd24: /* System Handler Control and State (SHCSR) */
if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
@ -1683,6 +1689,15 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
(cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK)
| (value & R_V7M_CCR_BFHFNMIGN_MASK);
value &= ~R_V7M_CCR_BFHFNMIGN_MASK;
} else {
/*
* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0, so
* preserve the state currently in the NS element of the array
*/
if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
value &= ~R_V7M_CCR_BFHFNMIGN_MASK;
value |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
}
}
cpu->env.v7m.ccr[attrs.secure] = value;