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SH4: Eliminate P4 to A7 mangling (Takashi YOSHII). 

Main purpose of this is to delete
       *physical = address & 0x1fffffff;
at target-sh4/helper.c:449, using new mmio rule introduced by #5849
This masking is a nice trick to realize P4/A7 duality of SH registers.
But, IMHO, it is logically wrong.

Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have
one more address called A7 which is usually P4 address with upper 3bits masked.
This is an address only appears in TLB's physical address part.

Current code use trick writing drivers as if they are really in A7
(that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2008-12-07 19:39:58 +00:00
parent 486579de70
commit 5c16736a37
6 changed files with 18 additions and 16 deletions
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3
hw/sh.h
View File

@ -4,6 +4,9 @@
#include "sh_intc.h"
#define A7ADDR(x) ((x) & 0x1fffffff)
#define P4ADDR(x) ((x) | 0xe0000000)
/* sh7750.c */
struct SH7750State;

6
hw/sh7750.c
View File

@ -683,10 +683,16 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
sh7750_mem_write, s);
cpu_register_physical_memory_offset(0x1f000000, 0x1000,
sh7750_io_memory, 0x1f000000);
cpu_register_physical_memory_offset(0xff000000, 0x1000,
sh7750_io_memory, 0x1f000000);
cpu_register_physical_memory_offset(0x1f800000, 0x1000,
sh7750_io_memory, 0x1f800000);
cpu_register_physical_memory_offset(0xff800000, 0x1000,
sh7750_io_memory, 0x1f800000);
cpu_register_physical_memory_offset(0x1fc00000, 0x1000,
sh7750_io_memory, 0x1fc00000);
cpu_register_physical_memory_offset(0xffc00000, 0x1000,
sh7750_io_memory, 0x1fc00000);
sh7750_mm_cache_and_tlb = cpu_register_io_memory(0,
sh7750_mmct_read,

7
hw/sh_intc.c
View File

@ -307,9 +307,12 @@ struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
static void sh_intc_register(struct intc_desc *desc,
unsigned long address)
{
if (address)
cpu_register_physical_memory_offset(INTC_A7(address), 4,
if (address) {
cpu_register_physical_memory_offset(P4ADDR(address), 4,
desc->iomemtype, INTC_A7(address));
cpu_register_physical_memory_offset(A7ADDR(address), 4,
desc->iomemtype, INTC_A7(address));
}
}
static void sh_intc_register_source(struct intc_desc *desc,

3
hw/sh_serial.c
View File

@ -399,7 +399,8 @@ void sh_serial_init (target_phys_addr_t base, int feat,
s_io_memory = cpu_register_io_memory(0, sh_serial_readfn,
sh_serial_writefn, s);
cpu_register_physical_memory(base, 0x28, s_io_memory);
cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);
s->chr = chr;

3
hw/sh_timer.c
View File

@ -320,6 +320,7 @@ void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
ch2_irq0); /* ch2_irq1 not supported */
iomemtype = cpu_register_io_memory(0, tmu012_readfn,
tmu012_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype);
cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype);
/* ??? Save/restore. */
}

12
target-sh4/helper.c
View File

@ -439,19 +439,7 @@ int get_physical_address(CPUState * env, target_ulong * physical,
if (address >= 0x80000000 && address < 0xc0000000) {
/* Mask upper 3 bits for P1 and P2 areas */
*physical = address & 0x1fffffff;
} else if (address >= 0xfd000000 && address < 0xfe000000) {
/* PCI memory space */
*physical = address;
} else if (address >= 0xfc000000) {
/*
* Mask upper 3 bits for control registers in P4 area,
* to unify access to control registers via P0-P3 area.
* The addresses for cache store queue, TLB address array
* are not masked.
*/
*physical = address & 0x1fffffff;
} else {
/* access to cache store queue, or TLB address array. */
*physical = address;
}
*prot = PAGE_READ | PAGE_WRITE;