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s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 

Use the new vector expansion for GVecGen3i.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
This commit is contained in:
David Hildenbrand 2019-04-11 11:27:29 +02:00
parent 55236da222
commit 5c4b0ab460
4 changed files with 75 additions and 0 deletions
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2
target/s390x/helper.h
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@ -202,6 +202,8 @@ DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)

2
target/s390x/insn-data.def
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@ -1149,6 +1149,8 @@
/* VECTOR ELEMENT ROTATE LEFT LOGICAL */
F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC)
F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC)
/* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */

51
target/s390x/translate_vx.inc.c
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@ -197,6 +197,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \
tcg_gen_gvec_3_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
#define gen_gvec_3i(v1, v2, v3, c, gen) \
tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), c, 16, 16, gen)
#define gen_gvec_4(v1, v2, v3, v4, gen) \
tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
@ -1905,3 +1908,51 @@ static DisasJumpType op_verll(DisasContext *s, DisasOps *o)
&g[es]);
return DISAS_NEXT;
}
static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c)
{
TCGv_i32 t = tcg_temp_new_i32();
tcg_gen_rotli_i32(t, a, c & 31);
tcg_gen_and_i32(t, t, b);
tcg_gen_andc_i32(d, d, b);
tcg_gen_or_i32(d, d, t);
tcg_temp_free_i32(t);
}
static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c)
{
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_rotli_i64(t, a, c & 63);
tcg_gen_and_i64(t, t, b);
tcg_gen_andc_i64(d, d, b);
tcg_gen_or_i64(d, d, t);
tcg_temp_free_i64(t);
}
static DisasJumpType op_verim(DisasContext *s, DisasOps *o)
{
const uint8_t es = get_field(s->fields, m5);
const uint8_t i4 = get_field(s->fields, i4) &
(NUM_VEC_ELEMENT_BITS(es) - 1);
static const GVecGen3i g[4] = {
{ .fno = gen_helper_gvec_verim8, },
{ .fno = gen_helper_gvec_verim16, },
{ .fni4 = gen_rim_i32,
.load_dest = true, },
{ .fni8 = gen_rim_i64,
.load_dest = true, },
};
if (es > ES_64) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
gen_gvec_3i(get_field(s->fields, v1), get_field(s->fields, v2),
get_field(s->fields, v3), i4, &g[es]);
return DISAS_NEXT;
}

20
target/s390x/vec_int_helper.c
View File

@ -14,6 +14,7 @@
#include "cpu.h"
#include "vec.h"
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
static bool s390_vec_is_zero(const S390Vector *v)
{
@ -509,3 +510,22 @@ void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, \
}
DEF_VERLL(8)
DEF_VERLL(16)
#define DEF_VERIM(BITS) \
void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3, \
uint32_t desc) \
{ \
const uint8_t count = simd_data(desc); \
int i; \
\
for (i = 0; i < (128 / BITS); i++) { \
const uint##BITS##_t a = s390_vec_read_element##BITS(v1, i); \
const uint##BITS##_t b = s390_vec_read_element##BITS(v2, i); \
const uint##BITS##_t mask = s390_vec_read_element##BITS(v3, i); \
const uint##BITS##_t d = (a & ~mask) | (rol##BITS(b, count) & mask); \
\
s390_vec_write_element##BITS(v1, i, d); \
} \
}
DEF_VERIM(8)
DEF_VERIM(16)