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target-microblaze: Correct special register array sizes 

Correct special register array sizes.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Edgar E. Iglesias 2018-04-13 21:55:21 +02:00
parent 4c8ac10737
commit 5c594ef3c7
2 changed files with 4 additions and 5 deletions
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4
target/microblaze/cpu.h
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@ -242,8 +242,8 @@ struct CPUMBState {
uint32_t bimm;
uint32_t imm;
uint32_t regs[33];
uint32_t sregs[24];
uint32_t regs[32];
uint32_t sregs[14];
float_status fp_status;
/* Stack protectors. Yes, it's a hw feature. */
uint32_t slr, shr;

5
target/microblaze/translate.c
View File

@ -54,7 +54,7 @@
static TCGv env_debug;
static TCGv cpu_R[32];
static TCGv cpu_SR[18];
static TCGv cpu_SR[14];
static TCGv env_imm;
static TCGv env_btaken;
static TCGv env_btarget;
@ -106,8 +106,7 @@ static const char *regnames[] =
static const char *special_regnames[] =
{
"rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
"sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
"sr16", "sr17", "sr18"
"sr8", "sr9", "sr10", "sr11", "sr12", "sr13"
};
static inline void t_sync_flags(DisasContext *dc)