OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

spapr: Rename xics to intc in interrupt controller agnostic code 

All this code is used with both the XICS and XIVE interrupt controllers.

Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Greg Kurz 2019-01-17 18:14:39 +01:00 committed by David Gibson
parent b39701db13
commit 5c7adcf422
6 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
hw/ppc/spapr.c
View File

@ -96,7 +96,7 @@
#define MIN_RMA_SLOF 128UL
#define PHANDLE_XICP 0x00001111
#define PHANDLE_INTC 0x00001111
/* These two functions implement the VCPU id numbering: one to compute them
* all and one to identify thread 0 of a VCORE. Any change to the first one
@ -1274,7 +1274,7 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr)
/* /interrupt controller */
spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt,
PHANDLE_XICP);
PHANDLE_INTC);
ret = spapr_populate_memory(spapr, fdt);
if (ret < 0) {
@ -1294,7 +1294,7 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr)
}
QLIST_FOREACH(phb, &spapr->phbs, list) {
ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt,
ret = spapr_populate_pci_dt(phb, PHANDLE_INTC, fdt,
spapr->irq->nr_msis);
if (ret < 0) {
error_report("couldn't setup PCI devices in fdt");

2
hw/ppc/spapr_events.c
View File

@ -282,7 +282,7 @@ void spapr_dt_events(sPAPRMachineState *spapr, void *fdt)
continue;
}
spapr_dt_xics_irq(interrupts, source->irq, false);
spapr_dt_irq(interrupts, source->irq, false);
_FDT(node_offset = fdt_add_subnode(fdt, event_sources, source_name));
_FDT(fdt_setprop(fdt, node_offset, "interrupts", interrupts,

6
hw/ppc/spapr_pci.c
View File

@ -2063,7 +2063,7 @@ static void spapr_phb_pci_enumerate(sPAPRPHBState *phb)
}
int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t xics_phandle, void *fdt,
int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t intc_phandle, void *fdt,
uint32_t nr_msis)
{
int bus_off, i, j, ret;
@ -2161,8 +2161,8 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t xics_phandle, void *fdt,
irqmap[1] = 0;
irqmap[2] = 0;
irqmap[3] = cpu_to_be32(j+1);
irqmap[4] = cpu_to_be32(xics_phandle);
spapr_dt_xics_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true);
irqmap[4] = cpu_to_be32(intc_phandle);
spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true);
}
}
/* Write interrupt map */

2
hw/ppc/spapr_vio.c
View File

@ -126,7 +126,7 @@ static int vio_make_devnode(VIOsPAPRDevice *dev,
if (dev->irq) {
uint32_t ints_prop[2];
spapr_dt_xics_irq(ints_prop, dev->irq, false);
spapr_dt_irq(ints_prop, dev->irq, false);
ret = fdt_setprop(fdt, node_off, "interrupts", ints_prop,
sizeof(ints_prop));
if (ret < 0) {

2
include/hw/pci-host/spapr.h
View File

@ -112,7 +112,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
return spapr_qirq(spapr, phb->lsi_table[pin].irq);
}
int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t xics_phandle, void *fdt,
int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t intc_phandle, void *fdt,
uint32_t nr_msis);
void spapr_pci_rtas_init(void);

2
include/hw/ppc/spapr.h
View File

@ -683,7 +683,7 @@ void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
* "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
* VIO devices, RTAS event sources and PHBs).
*/
static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi)
static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi)
{
intspec[0] = cpu_to_be32(irq);
intspec[1] = is_lsi ? cpu_to_be32(1) : 0;