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nvdimm: Use configurable ACPI IO base and size 

This patch makes IO base and size configurable to create NPIO AML for
ACPI NFIT. Since a different architecture like AArch64 does not use
port-mapped IO, a configurable IO base is required to create correct
mapping of ACPI IO address and size.

Signed-off-by: Kwangwoo Lee <kwangwoo.lee@sk.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20200421125934.14952-3-shameerali.kolothum.thodi@huawei.com>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Kwangwoo Lee 2020-04-21 13:59:29 +01:00 committed by Michael S. Tsirkin
parent 71b0269ae9
commit 5c94b82662
6 changed files with 38 additions and 10 deletions
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32
hw/acpi/nvdimm.c
View File

@ -900,11 +900,13 @@ void nvdimm_acpi_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev)
} }
void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io, void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io,
struct AcpiGenericAddress dsm_io,
FWCfgState *fw_cfg, Object *owner) FWCfgState *fw_cfg, Object *owner)
{ {
state->dsm_io = dsm_io;
memory_region_init_io(&state->io_mr, owner, &nvdimm_dsm_ops, state, memory_region_init_io(&state->io_mr, owner, &nvdimm_dsm_ops, state,
"nvdimm-acpi-io", NVDIMM_ACPI_IO_LEN); "nvdimm-acpi-io", dsm_io.bit_width >> 3);
memory_region_add_subregion(io, NVDIMM_ACPI_IO_BASE, &state->io_mr); memory_region_add_subregion(io, dsm_io.address, &state->io_mr);
state->dsm_mem = g_array_new(false, true /* clear */, 1); state->dsm_mem = g_array_new(false, true /* clear */, 1);
acpi_data_push(state->dsm_mem, sizeof(NvdimmDsmIn)); acpi_data_push(state->dsm_mem, sizeof(NvdimmDsmIn));
@ -933,13 +935,15 @@ void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io,
#define NVDIMM_QEMU_RSVD_UUID "648B9CF2-CDA1-4312-8AD9-49C4AF32BD62" #define NVDIMM_QEMU_RSVD_UUID "648B9CF2-CDA1-4312-8AD9-49C4AF32BD62"
static void nvdimm_build_common_dsm(Aml *dev) static void nvdimm_build_common_dsm(Aml *dev,
NVDIMMState *nvdimm_state)
{ {
Aml *method, *ifctx, *function, *handle, *uuid, *dsm_mem, *elsectx2; Aml *method, *ifctx, *function, *handle, *uuid, *dsm_mem, *elsectx2;
Aml *elsectx, *unsupport, *unpatched, *expected_uuid, *uuid_invalid; Aml *elsectx, *unsupport, *unpatched, *expected_uuid, *uuid_invalid;
Aml *pckg, *pckg_index, *pckg_buf, *field, *dsm_out_buf, *dsm_out_buf_size; Aml *pckg, *pckg_index, *pckg_buf, *field, *dsm_out_buf, *dsm_out_buf_size;
Aml *whilectx, *offset; Aml *whilectx, *offset;
uint8_t byte_list[1]; uint8_t byte_list[1];
AmlRegionSpace rs;
method = aml_method(NVDIMM_COMMON_DSM, 5, AML_SERIALIZED); method = aml_method(NVDIMM_COMMON_DSM, 5, AML_SERIALIZED);
uuid = aml_arg(0); uuid = aml_arg(0);
@ -950,9 +954,16 @@ static void nvdimm_build_common_dsm(Aml *dev)
aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), dsm_mem)); aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), dsm_mem));
if (nvdimm_state->dsm_io.space_id == AML_AS_SYSTEM_IO) {
rs = AML_SYSTEM_IO;
} else {
rs = AML_SYSTEM_MEMORY;
}
/* map DSM memory and IO into ACPI namespace. */ /* map DSM memory and IO into ACPI namespace. */
aml_append(method, aml_operation_region(NVDIMM_DSM_IOPORT, AML_SYSTEM_IO, aml_append(method, aml_operation_region(NVDIMM_DSM_IOPORT, rs,
aml_int(NVDIMM_ACPI_IO_BASE), NVDIMM_ACPI_IO_LEN)); aml_int(nvdimm_state->dsm_io.address),
nvdimm_state->dsm_io.bit_width >> 3));
aml_append(method, aml_operation_region(NVDIMM_DSM_MEMORY, aml_append(method, aml_operation_region(NVDIMM_DSM_MEMORY,
AML_SYSTEM_MEMORY, dsm_mem, sizeof(NvdimmDsmIn))); AML_SYSTEM_MEMORY, dsm_mem, sizeof(NvdimmDsmIn)));
@ -967,7 +978,7 @@ static void nvdimm_build_common_dsm(Aml *dev)
field = aml_field(NVDIMM_DSM_IOPORT, AML_DWORD_ACC, AML_NOLOCK, field = aml_field(NVDIMM_DSM_IOPORT, AML_DWORD_ACC, AML_NOLOCK,
AML_PRESERVE); AML_PRESERVE);
aml_append(field, aml_named_field(NVDIMM_DSM_NOTIFY, aml_append(field, aml_named_field(NVDIMM_DSM_NOTIFY,
NVDIMM_ACPI_IO_LEN * BITS_PER_BYTE)); nvdimm_state->dsm_io.bit_width));
aml_append(method, field); aml_append(method, field);
/* /*
@ -1268,7 +1279,8 @@ static void nvdimm_build_nvdimm_devices(Aml *root_dev, uint32_t ram_slots)
} }
static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data, static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data,
BIOSLinker *linker, GArray *dsm_dma_area, BIOSLinker *linker,
NVDIMMState *nvdimm_state,
uint32_t ram_slots) uint32_t ram_slots)
{ {
Aml *ssdt, *sb_scope, *dev; Aml *ssdt, *sb_scope, *dev;
@ -1296,7 +1308,7 @@ static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data,
*/ */
aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012"))); aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012")));
nvdimm_build_common_dsm(dev); nvdimm_build_common_dsm(dev, nvdimm_state);
/* 0 is reserved for root device. */ /* 0 is reserved for root device. */
nvdimm_build_device_dsm(dev, 0); nvdimm_build_device_dsm(dev, 0);
@ -1315,7 +1327,7 @@ static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data,
NVDIMM_ACPI_MEM_ADDR); NVDIMM_ACPI_MEM_ADDR);
bios_linker_loader_alloc(linker, bios_linker_loader_alloc(linker,
NVDIMM_DSM_MEM_FILE, dsm_dma_area, NVDIMM_DSM_MEM_FILE, nvdimm_state->dsm_mem,
sizeof(NvdimmDsmIn), false /* high memory */); sizeof(NvdimmDsmIn), false /* high memory */);
bios_linker_loader_add_pointer(linker, bios_linker_loader_add_pointer(linker,
ACPI_BUILD_TABLE_FILE, mem_addr_offset, sizeof(uint32_t), ACPI_BUILD_TABLE_FILE, mem_addr_offset, sizeof(uint32_t),
@ -1337,7 +1349,7 @@ void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
return; return;
} }
nvdimm_build_ssdt(table_offsets, table_data, linker, state->dsm_mem, nvdimm_build_ssdt(table_offsets, table_data, linker, state,
ram_slots); ram_slots);
device_list = nvdimm_get_device_list(); device_list = nvdimm_get_device_list();

6
hw/i386/acpi-build.c
View File

@ -128,6 +128,12 @@ typedef struct FwCfgTPMConfig {
static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
.space_id = AML_AS_SYSTEM_IO,
.address = NVDIMM_ACPI_IO_BASE,
.bit_width = NVDIMM_ACPI_IO_LEN << 3
};
static void init_common_fadt_data(MachineState *ms, Object *o, static void init_common_fadt_data(MachineState *ms, Object *o,
AcpiFadtData *data) AcpiFadtData *data)
{ {

3
hw/i386/acpi-build.h
View File

@ -1,6 +1,9 @@
#ifndef HW_I386_ACPI_BUILD_H #ifndef HW_I386_ACPI_BUILD_H
#define HW_I386_ACPI_BUILD_H #define HW_I386_ACPI_BUILD_H
#include "hw/acpi/acpi-defs.h"
extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio;
void acpi_setup(void); void acpi_setup(void);

2
hw/i386/pc_piix.c
View File

@ -61,6 +61,7 @@
#include "migration/misc.h" #include "migration/misc.h"
#include "sysemu/numa.h" #include "sysemu/numa.h"
#include "hw/mem/nvdimm.h" #include "hw/mem/nvdimm.h"
#include "hw/i386/acpi-build.h"
#define MAX_IDE_BUS 2 #define MAX_IDE_BUS 2
@ -297,6 +298,7 @@ static void pc_init1(MachineState *machine,
if (machine->nvdimms_state->is_enabled) { if (machine->nvdimms_state->is_enabled) {
nvdimm_init_acpi_state(machine->nvdimms_state, system_io, nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
x86_nvdimm_acpi_dsmio,
x86ms->fw_cfg, OBJECT(pcms)); x86ms->fw_cfg, OBJECT(pcms));
} }
} }

2
hw/i386/pc_q35.c
View File

@ -54,6 +54,7 @@
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "sysemu/numa.h" #include "sysemu/numa.h"
#include "hw/mem/nvdimm.h" #include "hw/mem/nvdimm.h"
#include "hw/i386/acpi-build.h"
/* ICH9 AHCI has 6 ports */ /* ICH9 AHCI has 6 ports */
#define MAX_SATA_PORTS 6 #define MAX_SATA_PORTS 6
@ -315,6 +316,7 @@ static void pc_q35_init(MachineState *machine)
if (machine->nvdimms_state->is_enabled) { if (machine->nvdimms_state->is_enabled) {
nvdimm_init_acpi_state(machine->nvdimms_state, system_io, nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
x86_nvdimm_acpi_dsmio,
x86ms->fw_cfg, OBJECT(pcms)); x86ms->fw_cfg, OBJECT(pcms));
} }
} }

3
include/hw/mem/nvdimm.h
View File

@ -26,6 +26,7 @@
#include "hw/mem/pc-dimm.h" #include "hw/mem/pc-dimm.h"
#include "hw/acpi/bios-linker-loader.h" #include "hw/acpi/bios-linker-loader.h"
#include "qemu/uuid.h" #include "qemu/uuid.h"
#include "hw/acpi/aml-build.h"
#define NVDIMM_DEBUG 0 #define NVDIMM_DEBUG 0
#define nvdimm_debug(fmt, ...) \ #define nvdimm_debug(fmt, ...) \
@ -147,10 +148,12 @@ struct NVDIMMState {
*/ */
int32_t persistence; int32_t persistence;
char *persistence_string; char *persistence_string;
struct AcpiGenericAddress dsm_io;
}; };
typedef struct NVDIMMState NVDIMMState; typedef struct NVDIMMState NVDIMMState;
void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io, void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io,
struct AcpiGenericAddress dsm_io,
FWCfgState *fw_cfg, Object *owner); FWCfgState *fw_cfg, Object *owner);
void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
BIOSLinker *linker, NVDIMMState *state, BIOSLinker *linker, NVDIMMState *state,