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target/riscv: Fix mcycle/minstret increment behavior

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The mcycle/minstret counter's stop flag is mistakenly updated on a copy
on stack. Thus the counter increments even when the CY/IR bit in the
mcountinhibit register is set. This commit corrects its behavior.

Fixes: 3780e33732f88 (target/riscv: Support mcycle/minstret write operation)
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Xu Lu 2023-12-26 12:05:00 +08:00 committed by Michael Tokarev
parent 0c1eccd368
commit 5cb0e7abe1
1 changed files with 7 additions and 7 deletions
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14
target/riscv/csr.c
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@ -907,11 +907,11 @@ static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
bool upper_half, uint32_t ctr_idx) bool upper_half, uint32_t ctr_idx)
{ {
PMUCTRState counter = env->pmu_ctrs[ctr_idx]; PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
target_ulong ctr_prev = upper_half ? counter.mhpmcounterh_prev : target_ulong ctr_prev = upper_half ? counter->mhpmcounterh_prev :
counter.mhpmcounter_prev; counter->mhpmcounter_prev;
target_ulong ctr_val = upper_half ? counter.mhpmcounterh_val : target_ulong ctr_val = upper_half ? counter->mhpmcounterh_val :
counter.mhpmcounter_val; counter->mhpmcounter_val;
if (get_field(env->mcountinhibit, BIT(ctr_idx))) { if (get_field(env->mcountinhibit, BIT(ctr_idx))) {
/* /*
@ -919,12 +919,12 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
* stop the icount counting. Just return the counter value written by * stop the icount counting. Just return the counter value written by
* the supervisor to indicate that counter was not incremented. * the supervisor to indicate that counter was not incremented.
*/ */
if (!counter.started) { if (!counter->started) {
*val = ctr_val; *val = ctr_val;
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} else { } else {
/* Mark that the counter has been stopped */ /* Mark that the counter has been stopped */
counter.started = false; counter->started = false;
} }
} }