target-ppc: Add VSX ISA2.06 xtsqrt Instructions
This patch adds the VSX floating point test for software square root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp, xvtsqrtdp, xvtsqrtsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Tom Musta
Alexander Graf
parent
bc80838f86
commit
5cb151acb1
@ -2095,3 +2095,57 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
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VSX_TDIV(xstdivdp, 1, float64, f64, -1022, 1023, 52)
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VSX_TDIV(xvtdivdp, 2, float64, f64, -1022, 1023, 52)
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VSX_TDIV(xvtdivsp, 4, float32, f32, -126, 127, 23)
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/* VSX_TSQRT - VSX floating point test for square root
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* op - instruction mnemonic
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* nels - number of elements (1, 2 or 4)
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* tp - type (float32 or float64)
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* fld - vsr_t field (f32 or f64)
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* emin - minimum unbiased exponent
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* emax - maximum unbiased exponent
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* nbits - number of fraction bits
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*/
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#define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
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void helper_##op(CPUPPCState *env, uint32_t opcode) \
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{ \
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ppc_vsr_t xa, xb; \
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int i; \
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int fe_flag = 0; \
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int fg_flag = 0; \
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\
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getVSR(xA(opcode), &xa, env); \
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getVSR(xB(opcode), &xb, env); \
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\
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for (i = 0; i < nels; i++) { \
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if (unlikely(tp##_is_infinity(xb.fld[i]) || \
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tp##_is_zero(xb.fld[i]))) { \
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fe_flag = 1; \
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fg_flag = 1; \
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} else { \
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int e_b = ppc_##tp##_get_unbiased_exp(xb.fld[i]); \
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\
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if (unlikely(tp##_is_any_nan(xb.fld[i]))) { \
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fe_flag = 1; \
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} else if (unlikely(tp##_is_zero(xb.fld[i]))) { \
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fe_flag = 1; \
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} else if (unlikely(tp##_is_neg(xb.fld[i]))) { \
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fe_flag = 1; \
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} else if (!tp##_is_zero(xb.fld[i]) && \
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(e_b <= (emin+nbits))) { \
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fe_flag = 1; \
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} \
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\
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if (unlikely(tp##_is_zero_or_denormal(xb.fld[i]))) { \
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/* XB is not zero because of the above check and */ \
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/* therefore must be denormalized. */ \
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fg_flag = 1; \
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} \
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} \
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} \
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\
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env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
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}
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VSX_TSQRT(xstsqrtdp, 1, float64, f64, -1022, 52)
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VSX_TSQRT(xvtsqrtdp, 2, float64, f64, -1022, 52)
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VSX_TSQRT(xvtsqrtsp, 4, float32, f32, -126, 23)
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@ -259,6 +259,7 @@ DEF_HELPER_2(xsredp, void, env, i32)
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DEF_HELPER_2(xssqrtdp, void, env, i32)
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DEF_HELPER_2(xsrsqrtedp, void, env, i32)
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DEF_HELPER_2(xstdivdp, void, env, i32)
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DEF_HELPER_2(xstsqrtdp, void, env, i32)
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DEF_HELPER_2(xvadddp, void, env, i32)
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DEF_HELPER_2(xvsubdp, void, env, i32)
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@ -268,6 +269,7 @@ DEF_HELPER_2(xvredp, void, env, i32)
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DEF_HELPER_2(xvsqrtdp, void, env, i32)
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DEF_HELPER_2(xvrsqrtedp, void, env, i32)
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DEF_HELPER_2(xvtdivdp, void, env, i32)
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DEF_HELPER_2(xvtsqrtdp, void, env, i32)
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DEF_HELPER_2(xvaddsp, void, env, i32)
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DEF_HELPER_2(xvsubsp, void, env, i32)
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@ -277,6 +279,7 @@ DEF_HELPER_2(xvresp, void, env, i32)
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DEF_HELPER_2(xvsqrtsp, void, env, i32)
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DEF_HELPER_2(xvrsqrtesp, void, env, i32)
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DEF_HELPER_2(xvtdivsp, void, env, i32)
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DEF_HELPER_2(xvtsqrtsp, void, env, i32)
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DEF_HELPER_2(efscfsi, i32, env, i32)
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DEF_HELPER_2(efscfui, i32, env, i32)
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@ -7312,6 +7312,7 @@ GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
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@ -7321,6 +7322,7 @@ GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
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@ -7330,6 +7332,7 @@ GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
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GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
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#define VSX_LOGICAL(name, tcg_op) \
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static void glue(gen_, name)(DisasContext * ctx) \
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@ -10020,6 +10023,7 @@ GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
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GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
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GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
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GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
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GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
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GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
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GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
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@ -10029,6 +10033,7 @@ GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
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GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
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GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
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GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
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GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
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GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
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GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
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@ -10038,6 +10043,7 @@ GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
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GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
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GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
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GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
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GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
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#undef VSX_LOGICAL
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#define VSX_LOGICAL(name, opc2, opc3, fl2) \
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