target/i386: Fix andn instruction
In commit 7073fbada7
, the `andn` instruction
was implemented via `tcg_gen_andc` but passes the operands in the wrong
order:
- X86 defines `andn dest,src1,src2` as: dest = ~src1 & src2
- TCG defines `andc dest,src1,src2` as: dest = src1 & ~src2
The following simple test shows the issue:
#include <stdio.h>
#include <stdint.h>
int main(void) {
uint32_t ret = 0;
__asm (
"mov $0xFF00, %%ecx\n"
"mov $0x0F0F, %%eax\n"
"andn %%ecx, %%eax, %%ecx\n"
"mov %%ecx, %0\n"
: "=r" (ret));
printf("%08X\n", ret);
return 0;
}
This patch fixes the problem by simply swapping the order of the two last
arguments in `tcg_gen_andc_tl`.
Reported-by: Alexandro Sanchez Bach <alexandro@phi.nz>
Signed-off-by: Alexandro Sanchez Bach <alexandro@phi.nz>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
d69748463c
commit
5cd10051c2
|
@ -3802,7 +3802,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
|||
}
|
||||
ot = mo_64_32(s->dflag);
|
||||
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
|
||||
tcg_gen_andc_tl(cpu_T0, cpu_regs[s->vex_v], cpu_T0);
|
||||
tcg_gen_andc_tl(cpu_T0, cpu_T0, cpu_regs[s->vex_v]);
|
||||
gen_op_mov_reg_v(ot, reg, cpu_T0);
|
||||
gen_op_update1_cc();
|
||||
set_cc_op(s, CC_OP_LOGICB + ot);
|
||||
|
|
Loading…
Reference in New Issue