target-arm: Support multiple address spaces in page table walks
If we have a secure address space, use it in page table walks: when doing the physical accesses to read descriptors, make them through the correct address space. (The descriptor reads are the only direct physical accesses made in target-arm/ for CPUs which might have TrustZone.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -2003,6 +2003,15 @@ static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
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{
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return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
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}
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/* Return the AddressSpace to use for a memory access
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* (which depends on whether the access is S or NS, and whether
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* the board gave us a separate AddressSpace for S accesses).
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*/
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static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
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{
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return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
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}
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#endif
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#endif
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@ -6273,13 +6273,15 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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MemTxAttrs attrs = {};
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AddressSpace *as;
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attrs.secure = is_secure;
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as = arm_addressspace(cs, attrs);
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addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
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if (fi->s1ptw) {
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return 0;
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}
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return address_space_ldl(cs->as, addr, attrs, NULL);
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return address_space_ldl(as, addr, attrs, NULL);
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}
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static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
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@ -6289,13 +6291,15 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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MemTxAttrs attrs = {};
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AddressSpace *as;
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attrs.secure = is_secure;
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as = arm_addressspace(cs, attrs);
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addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
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if (fi->s1ptw) {
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return 0;
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}
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return address_space_ldq(cs->as, addr, attrs, NULL);
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return address_space_ldq(as, addr, attrs, NULL);
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}
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static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
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