target/riscv: Drop ftemp_new
Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Replace the few uses with tcg_temp_new_i64. Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
571f850722
commit
5d50945166
|
@ -106,9 +106,6 @@ typedef struct DisasContext {
|
|||
TCGv zero;
|
||||
/* Space for 3 operands plus 1 extra for address computation. */
|
||||
TCGv temp[4];
|
||||
/* Space for 4 operands(1 dest and <=3 src) for float point computation */
|
||||
TCGv_i64 ftemp[4];
|
||||
uint8_t nftemp;
|
||||
/* PointerMasking extension */
|
||||
bool pm_mask_enabled;
|
||||
bool pm_base_enabled;
|
||||
|
@ -431,12 +428,6 @@ static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh)
|
|||
}
|
||||
}
|
||||
|
||||
static TCGv_i64 ftemp_new(DisasContext *ctx)
|
||||
{
|
||||
assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp));
|
||||
return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64();
|
||||
}
|
||||
|
||||
static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
|
||||
{
|
||||
if (!ctx->cfg_ptr->ext_zfinx) {
|
||||
|
@ -450,7 +441,7 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
|
|||
case MXL_RV32:
|
||||
#ifdef TARGET_RISCV32
|
||||
{
|
||||
TCGv_i64 t = ftemp_new(ctx);
|
||||
TCGv_i64 t = tcg_temp_new_i64();
|
||||
tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]);
|
||||
return t;
|
||||
}
|
||||
|
@ -476,7 +467,7 @@ static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num)
|
|||
switch (get_xl(ctx)) {
|
||||
case MXL_RV32:
|
||||
{
|
||||
TCGv_i64 t = ftemp_new(ctx);
|
||||
TCGv_i64 t = tcg_temp_new_i64();
|
||||
tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
|
||||
return t;
|
||||
}
|
||||
|
@ -496,12 +487,12 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num)
|
|||
}
|
||||
|
||||
if (reg_num == 0) {
|
||||
return ftemp_new(ctx);
|
||||
return tcg_temp_new_i64();
|
||||
}
|
||||
|
||||
switch (get_xl(ctx)) {
|
||||
case MXL_RV32:
|
||||
return ftemp_new(ctx);
|
||||
return tcg_temp_new_i64();
|
||||
#ifdef TARGET_RISCV64
|
||||
case MXL_RV64:
|
||||
return cpu_gpr[reg_num];
|
||||
|
@ -1208,8 +1199,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
|
|||
ctx->cs = cs;
|
||||
ctx->ntemp = 0;
|
||||
memset(ctx->temp, 0, sizeof(ctx->temp));
|
||||
ctx->nftemp = 0;
|
||||
memset(ctx->ftemp, 0, sizeof(ctx->ftemp));
|
||||
ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
|
||||
ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
|
||||
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
|
||||
|
@ -1245,11 +1234,6 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
|
|||
ctx->temp[i] = NULL;
|
||||
}
|
||||
ctx->ntemp = 0;
|
||||
for (i = ctx->nftemp - 1; i >= 0; --i) {
|
||||
tcg_temp_free_i64(ctx->ftemp[i]);
|
||||
ctx->ftemp[i] = NULL;
|
||||
}
|
||||
ctx->nftemp = 0;
|
||||
|
||||
/* Only the first insn within a TB is allowed to cross a page boundary. */
|
||||
if (ctx->base.is_jmp == DISAS_NEXT) {
|
||||
|
|
Loading…
Reference in New Issue