Hexagon HVX (target/hexagon) helper overrides - vector loads
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
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Taylor Simpson
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b0c2c182b9
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5d67ff6c6c
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@ -532,4 +532,154 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
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tcg_gen_gvec_abs(MO_32, VdV_off, VuV_off, \
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sizeof(MMVector), sizeof(MMVector))
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/* Vector loads */
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#define fGEN_TCG_V6_vL32b_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32Ub_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_cur_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_tmp_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_nt_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_nt_cur_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_nt_tmp_pi(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32Ub_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_cur_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_tmp_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_nt_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_nt_cur_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_nt_tmp_ai(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_ppu(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32Ub_ppu(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_cur_ppu(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_tmp_ppu(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_nt_ppu(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_nt_cur_ppu(SHORTCODE) SHORTCODE
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#define fGEN_TCG_V6_vL32b_nt_tmp_ppu(SHORTCODE) SHORTCODE
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/* Predicated vector loads */
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#define fGEN_TCG_PRED_VEC_LOAD(GET_EA, PRED, DSTOFF, INC) \
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do { \
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TCGv LSB = tcg_temp_new(); \
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TCGLabel *false_label = gen_new_label(); \
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TCGLabel *end_label = gen_new_label(); \
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GET_EA; \
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PRED; \
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tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \
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tcg_temp_free(LSB); \
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gen_vreg_load(ctx, DSTOFF, EA, true); \
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INC; \
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tcg_gen_br(end_label); \
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gen_set_label(false_label); \
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tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \
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1 << insn->slot); \
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gen_set_label(end_label); \
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} while (0)
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#define fGEN_TCG_PRED_VEC_LOAD_pred_pi \
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fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \
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fEA_REG(RxV), \
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VdV_off, \
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fPM_I(RxV, siV * sizeof(MMVector)))
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#define fGEN_TCG_PRED_VEC_LOAD_npred_pi \
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fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \
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fEA_REG(RxV), \
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VdV_off, \
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fPM_I(RxV, siV * sizeof(MMVector)))
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#define fGEN_TCG_V6_vL32b_pred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_pi
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#define fGEN_TCG_V6_vL32b_npred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_pi
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#define fGEN_TCG_V6_vL32b_cur_pred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_pi
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#define fGEN_TCG_V6_vL32b_cur_npred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_pi
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#define fGEN_TCG_V6_vL32b_tmp_pred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_pi
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#define fGEN_TCG_V6_vL32b_tmp_npred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_pi
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#define fGEN_TCG_V6_vL32b_nt_pred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_pi
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#define fGEN_TCG_V6_vL32b_nt_npred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_pi
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#define fGEN_TCG_V6_vL32b_nt_cur_pred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_pi
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#define fGEN_TCG_V6_vL32b_nt_cur_npred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_pi
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#define fGEN_TCG_V6_vL32b_nt_tmp_pred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_pi
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#define fGEN_TCG_V6_vL32b_nt_tmp_npred_pi(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_pi
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#define fGEN_TCG_PRED_VEC_LOAD_pred_ai \
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fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \
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fEA_RI(RtV, siV * sizeof(MMVector)), \
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VdV_off, \
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do {} while (0))
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#define fGEN_TCG_PRED_VEC_LOAD_npred_ai \
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fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \
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fEA_RI(RtV, siV * sizeof(MMVector)), \
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VdV_off, \
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do {} while (0))
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#define fGEN_TCG_V6_vL32b_pred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ai
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#define fGEN_TCG_V6_vL32b_npred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ai
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#define fGEN_TCG_V6_vL32b_cur_pred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ai
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#define fGEN_TCG_V6_vL32b_cur_npred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ai
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#define fGEN_TCG_V6_vL32b_tmp_pred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ai
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#define fGEN_TCG_V6_vL32b_tmp_npred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ai
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#define fGEN_TCG_V6_vL32b_nt_pred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ai
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#define fGEN_TCG_V6_vL32b_nt_npred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ai
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#define fGEN_TCG_V6_vL32b_nt_cur_pred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ai
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#define fGEN_TCG_V6_vL32b_nt_cur_npred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ai
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#define fGEN_TCG_V6_vL32b_nt_tmp_pred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ai
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#define fGEN_TCG_V6_vL32b_nt_tmp_npred_ai(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ai
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#define fGEN_TCG_PRED_VEC_LOAD_pred_ppu \
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fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \
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fEA_REG(RxV), \
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VdV_off, \
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fPM_M(RxV, MuV))
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#define fGEN_TCG_PRED_VEC_LOAD_npred_ppu \
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fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \
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fEA_REG(RxV), \
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VdV_off, \
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fPM_M(RxV, MuV))
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#define fGEN_TCG_V6_vL32b_pred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ppu
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#define fGEN_TCG_V6_vL32b_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ppu
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#define fGEN_TCG_V6_vL32b_cur_pred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ppu
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#define fGEN_TCG_V6_vL32b_cur_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ppu
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#define fGEN_TCG_V6_vL32b_tmp_pred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ppu
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#define fGEN_TCG_V6_vL32b_tmp_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ppu
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#define fGEN_TCG_V6_vL32b_nt_pred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ppu
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#define fGEN_TCG_V6_vL32b_nt_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ppu
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#define fGEN_TCG_V6_vL32b_nt_cur_pred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ppu
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#define fGEN_TCG_V6_vL32b_nt_cur_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ppu
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#define fGEN_TCG_V6_vL32b_nt_tmp_pred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_pred_ppu
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#define fGEN_TCG_V6_vL32b_nt_tmp_npred_ppu(SHORTCODE) \
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fGEN_TCG_PRED_VEC_LOAD_npred_ppu
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#endif
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