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target/mips: Fix emulation of nanoMIPS BPOSGE32C instruction 

There are currently two problems related to the emulation of the
instruction BPOSGE32C.

The nanoMIPS instruction BPOSGE32C belongs to DSP R3 instructions
(actually, as of now, it is the only instruction of DSP R3). The
presence of DSP R3 instructions in QEMU is indicated by the flag
MIPS_HFLAG_DSP_R3 (0x20000000). This flag is currently being properly
set in CPUMIPSState's hflags (for example, for I7200 nanoMIPS CPU).
However, it is not propagated to DisasContext's hflags, since the flag
MIPS_HFLAG_DSP_R3 is not set in MIPS_HFLAG_TMASK (while similar flags
MIPS_HFLAG_DSP_R2 and MIPS_HFLAG_DSP are set in this mask, and there
is no problem in functioning check_dsp_r2(), check_dsp()). This means
the function check_dsp_r3() currently does not work properly, and the
emulation of BPOSGE32C can not work properly as well.

Change MIPS_HFLAG_TMASK from 0x1F5807FF to 0x3F5807FF (logical OR
with 0x20000000) to fix this.

Additionally, check_cp1_enabled() is currently incorrectly called
while emulating BPOSGE32C. BPOSGE32C is in the same pool (P.BR1) as
FPU branch instruction BC1EQZC and BC1NEZC, but it not a part of FPU
(CP1) instructions, and check_cp1_enabled() should not be involved
while emulating BPOSGE32C.

Rearrange invocations of check_cp1_enabled() within P.BR1 pool
handling to affect only BC1EQZC and BC1NEZC emulation, and not
BPOSGE32C emulation.

Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220504110403.613168-4-stefan.pejic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Dragan Mladjenovic 2022-05-04 13:03:59 +02:00 committed by Philippe Mathieu-Daudé
parent 9e4f726d4f
commit 5de4359b4f
2 changed files with 3 additions and 2 deletions
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2
target/mips/cpu.h
View File

@ -1077,7 +1077,7 @@ typedef struct CPUArchState {
#define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
uint32_t hflags; /* CPU State */ uint32_t hflags; /* CPU State */
/* TMASK defines different execution modes */ /* TMASK defines different execution modes */
#define MIPS_HFLAG_TMASK 0x1F5807FF #define MIPS_HFLAG_TMASK 0x3F5807FF
#define MIPS_HFLAG_MODE 0x00007 /* execution modes */ #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
/* /*
* The KSU flags must be the lowest bits in hflags. The flag order * The KSU flags must be the lowest bits in hflags. The flag order

3
target/mips/tcg/nanomips_translate.c.inc
View File

@ -4478,12 +4478,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P_BR3A: case NM_P_BR3A:
s = sextract32(ctx->opcode, 0, 1) << 14 | s = sextract32(ctx->opcode, 0, 1) << 14 |
extract32(ctx->opcode, 1, 13) << 1; extract32(ctx->opcode, 1, 13) << 1;
check_cp1_enabled(ctx);
switch (extract32(ctx->opcode, 16, 5)) { switch (extract32(ctx->opcode, 16, 5)) {
case NM_BC1EQZC: case NM_BC1EQZC:
check_cp1_enabled(ctx);
gen_compute_branch_cp1_nm(ctx, OPC_BC1EQZ, rt, s); gen_compute_branch_cp1_nm(ctx, OPC_BC1EQZ, rt, s);
break; break;
case NM_BC1NEZC: case NM_BC1NEZC:
check_cp1_enabled(ctx);
gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s); gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
break; break;
case NM_BPOSGE32C: case NM_BPOSGE32C: